Lines Matching defs:drm_amdgpu_info_device

1080 struct drm_amdgpu_info_device {  struct
1082 	__u32 device_id;
1084 	__u32 chip_rev;
1085 	__u32 external_rev;
1087 	__u32 pci_rev;
1088 	__u32 family;
1089 	__u32 num_shader_engines;
1090 	__u32 num_shader_arrays_per_engine;
1092 	__u32 gpu_counter_freq;
1093 	__u64 max_engine_clock;
1094 	__u64 max_memory_clock;
1096 	__u32 cu_active_number;
1098 	__u32 cu_ao_mask;
1099 	__u32 cu_bitmap[4][4];
1101 	__u32 enabled_rb_pipes_mask;
1102 	__u32 num_rb_pipes;
1103 	__u32 num_hw_gfx_contexts;
1105 	__u32 pcie_gen;
1106 	__u64 ids_flags;
1108 	__u64 virtual_address_offset;
1110 	__u64 virtual_address_max;
1112 	__u32 virtual_address_alignment;
1114 	__u32 pte_fragment_size;
1115 	__u32 gart_page_size;
1117 	__u32 ce_ram_size;
1119 	__u32 vram_type;
1121 	__u32 vram_bit_width;
1123 	__u32 vce_harvest_config;
1125 	__u32 gc_double_offchip_lds_buf;
1127 	__u64 prim_buf_gpu_addr;
1129 	__u64 pos_buf_gpu_addr;
1131 	__u64 cntl_sb_buf_gpu_addr;
1133 	__u64 param_buf_gpu_addr;
1134 	__u32 prim_buf_size;
1135 	__u32 pos_buf_size;
1136 	__u32 cntl_sb_buf_size;
1137 	__u32 param_buf_size;
1139 	__u32 wave_front_size;
1141 	__u32 num_shader_visible_vgprs;
1143 	__u32 num_cu_per_sh;
1145 	__u32 num_tcc_blocks;
1147 	__u32 gs_vgt_table_depth;
1149 	__u32 gs_prim_buffer_depth;
1151 	__u32 max_gs_waves_per_vgt;
1153 	__u32 pcie_num_lanes;
1155 	__u32 cu_ao_bitmap[4][4];
1157 	__u64 high_va_offset;
1159 	__u64 high_va_max;
1161 	__u32 pa_sc_tile_steering_override;
1163 	__u64 tcc_disabled_mask;
1164 	__u64 min_engine_clock;
1165 	__u64 min_memory_clock;
1167 	__u32 tcp_cache_size;       /* AKA GL0, VMEM cache */
1168 	__u32 num_sqc_per_wgp;
1169 	__u32 sqc_data_cache_size;  /* AKA SMEM cache */
1170 	__u32 sqc_inst_cache_size;
1171 	__u32 gl1c_cache_size;
1172 	__u32 gl2c_cache_size;
1173 	__u64 mall_size;            /* AKA infinity cache */
1175 	__u32 enabled_rb_pipes_mask_hi;
1177 	__u32 shadow_size;
1179 	__u32 shadow_alignment;
1181 	__u32 csa_size;
1183 	__u32 csa_alignment;