Lines Matching +full:0 +full:x2500
15 #define CS42L42_PAGE_REGISTER 0x00 /* Page Select Register */
16 #define CS42L42_WIN_START 0x00
17 #define CS42L42_WIN_LEN 0x100
18 #define CS42L42_RANGE_MIN 0x00
19 #define CS42L42_RANGE_MAX 0x7F
21 #define CS42L42_PAGE_10 0x1000
22 #define CS42L42_PAGE_11 0x1100
23 #define CS42L42_PAGE_12 0x1200
24 #define CS42L42_PAGE_13 0x1300
25 #define CS42L42_PAGE_15 0x1500
26 #define CS42L42_PAGE_19 0x1900
27 #define CS42L42_PAGE_1B 0x1B00
28 #define CS42L42_PAGE_1C 0x1C00
29 #define CS42L42_PAGE_1D 0x1D00
30 #define CS42L42_PAGE_1F 0x1F00
31 #define CS42L42_PAGE_20 0x2000
32 #define CS42L42_PAGE_21 0x2100
33 #define CS42L42_PAGE_23 0x2300
34 #define CS42L42_PAGE_24 0x2400
35 #define CS42L42_PAGE_25 0x2500
36 #define CS42L42_PAGE_26 0x2600
37 #define CS42L42_PAGE_27 0x2700
38 #define CS42L42_PAGE_28 0x2800
39 #define CS42L42_PAGE_29 0x2900
40 #define CS42L42_PAGE_2A 0x2A00
41 #define CS42L42_PAGE_30 0x3000
43 #define CS42L42_CHIP_ID 0x42A42
44 #define CS42L83_CHIP_ID 0x42A83
46 /* Page 0x10 Global Registers */
47 #define CS42L42_DEVID_AB (CS42L42_PAGE_10 + 0x01)
48 #define CS42L42_DEVID_CD (CS42L42_PAGE_10 + 0x02)
49 #define CS42L42_DEVID_E (CS42L42_PAGE_10 + 0x03)
50 #define CS42L42_FABID (CS42L42_PAGE_10 + 0x04)
51 #define CS42L42_REVID (CS42L42_PAGE_10 + 0x05)
52 #define CS42L42_FRZ_CTL (CS42L42_PAGE_10 + 0x06)
54 #define CS42L42_SRC_CTL (CS42L42_PAGE_10 + 0x07)
58 #define CS42L42_MCLK_STATUS (CS42L42_PAGE_10 + 0x08)
60 #define CS42L42_MCLK_CTL (CS42L42_PAGE_10 + 0x09)
64 #define CS42L42_SFTRAMP_RATE (CS42L42_PAGE_10 + 0x0A)
65 #define CS42L42_SLOW_START_ENABLE (CS42L42_PAGE_10 + 0x0B)
68 #define CS42L42_I2C_DEBOUNCE (CS42L42_PAGE_10 + 0x0E)
69 #define CS42L42_I2C_STRETCH (CS42L42_PAGE_10 + 0x0F)
70 #define CS42L42_I2C_TIMEOUT (CS42L42_PAGE_10 + 0x10)
72 /* Page 0x11 Power and Headset Detect Registers */
73 #define CS42L42_PWR_CTL1 (CS42L42_PAGE_11 + 0x01)
86 #define CS42L42_PDN_ALL_SHIFT 0
89 #define CS42L42_PWR_CTL2 (CS42L42_PAGE_11 + 0x02)
90 #define CS42L42_ADC_SRC_PDNB_SHIFT 0
101 #define CS42L42_PWR_CTL3 (CS42L42_PAGE_11 + 0x03)
109 #define CS42L42_RSENSE_CTL1 (CS42L42_PAGE_11 + 0x04)
110 #define CS42L42_RS_TRIM_R_SHIFT 0
121 #define CS42L42_RSENSE_CTL2 (CS42L42_PAGE_11 + 0x05)
125 #define CS42L42_OSC_SWITCH (CS42L42_PAGE_11 + 0x07)
126 #define CS42L42_SCLK_PRESENT_SHIFT 0
129 #define CS42L42_OSC_SWITCH_STATUS (CS42L42_PAGE_11 + 0x09)
130 #define CS42L42_OSC_SW_SEL_STAT_SHIFT 0
135 #define CS42L42_RSENSE_CTL3 (CS42L42_PAGE_11 + 0x12)
136 #define CS42L42_RS_RISE_DBNCE_TIME_SHIFT 0
145 #define CS42L42_TSENSE_CTL (CS42L42_PAGE_11 + 0x13)
146 #define CS42L42_TS_RISE_DBNCE_TIME_SHIFT 0
153 #define CS42L42_TSRS_INT_DISABLE (CS42L42_PAGE_11 + 0x14)
154 #define CS42L42_D_RS_PLUG_DBNC_SHIFT 0
163 #define CS42L42_TRSENSE_STATUS (CS42L42_PAGE_11 + 0x15)
164 #define CS42L42_RS_PLUG_DBNC_SHIFT 0
173 #define CS42L42_HSDET_CTL1 (CS42L42_PAGE_11 + 0x1F)
174 #define CS42L42_HSDET_COMP1_LVL_SHIFT 0
184 #define CS42L42_HSDET_CTL2 (CS42L42_PAGE_11 + 0x20)
185 #define CS42L42_HSDET_AUTO_TIME_SHIFT 0
194 #define CS42L42_HS_SWITCH_CTL (CS42L42_PAGE_11 + 0x21)
195 #define CS42L42_SW_GNDHS_HS4_SHIFT 0
212 #define CS42L42_HS_DET_STATUS (CS42L42_PAGE_11 + 0x24)
213 #define CS42L42_HSDET_TYPE_SHIFT 0
219 #define CS42L42_PLUG_CTIA 0
224 #define CS42L42_HSDET_SW_COMP1 ((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \
227 (0 << CS42L42_SW_HSB_HS3_SHIFT) | \
228 (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \
230 (0 << CS42L42_SW_REF_HS4_SHIFT) | \
233 (0 << CS42L42_SW_GNDHS_HS3_SHIFT) | \
234 (0 << CS42L42_SW_HSB_HS4_SHIFT) | \
237 (0 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \
239 (0 << CS42L42_SW_REF_HS3_SHIFT))
240 #define CS42L42_HSDET_SW_TYPE1 ((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \
243 (0 << CS42L42_SW_HSB_HS3_SHIFT) | \
244 (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \
246 (0 << CS42L42_SW_REF_HS4_SHIFT) | \
249 (0 << CS42L42_SW_GNDHS_HS3_SHIFT) | \
250 (0 << CS42L42_SW_HSB_HS4_SHIFT) | \
253 (0 << CS42L42_SW_HSB_FILT_HS3_SHIFT) | \
255 (0 << CS42L42_SW_REF_HS3_SHIFT))
258 (0 << CS42L42_SW_HSB_HS4_SHIFT) | \
259 (0 << CS42L42_SW_HSB_HS3_SHIFT) | \
264 #define CS42L42_HSDET_SW_TYPE4 ((0 << CS42L42_SW_GNDHS_HS4_SHIFT) | \
267 (0 << CS42L42_SW_HSB_HS3_SHIFT) | \
268 (0 << CS42L42_SW_HSB_FILT_HS4_SHIFT) | \
270 (0 << CS42L42_SW_REF_HS4_SHIFT) | \
275 #define CS42L42_HSDET_COMP_TYPE3 0
278 #define CS42L42_HS_CLAMP_DISABLE (CS42L42_PAGE_11 + 0x29)
279 #define CS42L42_HS_CLAMP_DISABLE_SHIFT 0
282 /* Page 0x12 Clocking Registers */
283 #define CS42L42_MCLK_SRC_SEL (CS42L42_PAGE_12 + 0x01)
286 #define CS42L42_MCLK_SRC_SEL_SHIFT 0
289 #define CS42L42_SPDIF_CLK_CFG (CS42L42_PAGE_12 + 0x02)
290 #define CS42L42_FSYNC_PW_LOWER (CS42L42_PAGE_12 + 0x03)
292 #define CS42L42_FSYNC_PW_UPPER (CS42L42_PAGE_12 + 0x04)
293 #define CS42L42_FSYNC_PULSE_WIDTH_SHIFT 0
294 #define CS42L42_FSYNC_PULSE_WIDTH_MASK (0xff << \
297 #define CS42L42_FSYNC_P_LOWER (CS42L42_PAGE_12 + 0x05)
299 #define CS42L42_FSYNC_P_UPPER (CS42L42_PAGE_12 + 0x06)
300 #define CS42L42_FSYNC_PERIOD_SHIFT 0
301 #define CS42L42_FSYNC_PERIOD_MASK (0xff << CS42L42_FSYNC_PERIOD_SHIFT)
303 #define CS42L42_ASP_CLK_CFG (CS42L42_PAGE_12 + 0x07)
306 #define CS42L42_ASP_MASTER_MODE 0x01
307 #define CS42L42_ASP_SLAVE_MODE 0x00
313 #define CS42L42_ASP_LCPOL_SHIFT 0
317 #define CS42L42_ASP_FRM_CFG (CS42L42_PAGE_12 + 0x08)
322 #define CS42L42_ASP_FSD_SHIFT 0
329 #define CS42L42_FS_RATE_EN (CS42L42_PAGE_12 + 0x09)
330 #define CS42L42_FS_EN_SHIFT 0
331 #define CS42L42_FS_EN_MASK (0xf << CS42L42_FS_EN_SHIFT)
332 #define CS42L42_FS_EN_IASRC_96K 0x1
333 #define CS42L42_FS_EN_OASRC_96K 0x2
335 #define CS42L42_IN_ASRC_CLK (CS42L42_PAGE_12 + 0x0A)
336 #define CS42L42_CLK_IASRC_SEL_SHIFT 0
338 #define CS42L42_CLK_IASRC_SEL_6 0
341 #define CS42L42_OUT_ASRC_CLK (CS42L42_PAGE_12 + 0x0B)
342 #define CS42L42_CLK_OASRC_SEL_SHIFT 0
346 #define CS42L42_PLL_DIV_CFG1 (CS42L42_PAGE_12 + 0x0C)
347 #define CS42L42_SCLK_PREDIV_SHIFT 0
350 /* Page 0x13 Interrupt Registers */
352 #define CS42L42_ADC_OVFL_STATUS (CS42L42_PAGE_13 + 0x01)
353 #define CS42L42_MIXER_STATUS (CS42L42_PAGE_13 + 0x02)
354 #define CS42L42_SRC_STATUS (CS42L42_PAGE_13 + 0x03)
355 #define CS42L42_ASP_RX_STATUS (CS42L42_PAGE_13 + 0x04)
356 #define CS42L42_ASP_TX_STATUS (CS42L42_PAGE_13 + 0x05)
357 #define CS42L42_CODEC_STATUS (CS42L42_PAGE_13 + 0x08)
358 #define CS42L42_DET_INT_STATUS1 (CS42L42_PAGE_13 + 0x09)
359 #define CS42L42_DET_INT_STATUS2 (CS42L42_PAGE_13 + 0x0A)
360 #define CS42L42_SRCPL_INT_STATUS (CS42L42_PAGE_13 + 0x0B)
361 #define CS42L42_VPMON_STATUS (CS42L42_PAGE_13 + 0x0D)
362 #define CS42L42_PLL_LOCK_STATUS (CS42L42_PAGE_13 + 0x0E)
363 #define CS42L42_TSRS_PLUG_STATUS (CS42L42_PAGE_13 + 0x0F)
365 #define CS42L42_ADC_OVFL_INT_MASK (CS42L42_PAGE_13 + 0x16)
366 #define CS42L42_ADC_OVFL_SHIFT 0
370 #define CS42L42_MIXER_INT_MASK (CS42L42_PAGE_13 + 0x17)
371 #define CS42L42_MIX_CHB_OVFL_SHIFT 0
384 #define CS42L42_SRC_INT_MASK (CS42L42_PAGE_13 + 0x18)
385 #define CS42L42_SRC_ILK_SHIFT 0
398 #define CS42L42_ASP_RX_INT_MASK (CS42L42_PAGE_13 + 0x19)
399 #define CS42L42_ASPRX_NOLRCK_SHIFT 0
415 #define CS42L42_ASP_TX_INT_MASK (CS42L42_PAGE_13 + 0x1A)
416 #define CS42L42_ASPTX_NOLRCK_SHIFT 0
429 #define CS42L42_CODEC_INT_MASK (CS42L42_PAGE_13 + 0x1B)
430 #define CS42L42_PDN_DONE_SHIFT 0
437 #define CS42L42_SRCPL_INT_MASK (CS42L42_PAGE_13 + 0x1C)
438 #define CS42L42_SRCPL_ADC_LK_SHIFT 0
451 #define CS42L42_VPMON_INT_MASK (CS42L42_PAGE_13 + 0x1E)
452 #define CS42L42_VPMON_SHIFT 0
456 #define CS42L42_PLL_LOCK_INT_MASK (CS42L42_PAGE_13 + 0x1F)
457 #define CS42L42_PLL_LOCK_SHIFT 0
461 #define CS42L42_TSRS_PLUG_INT_MASK (CS42L42_PAGE_13 + 0x20)
462 #define CS42L42_RS_PLUG_SHIFT 0
475 #define CS42L42_TS_UNPLUG 0
479 * NOTE: PLL_START must be 0 while both ADC_PDN=1 and HP_PDN=1.
482 #define CS42L42_PLL_CTL1 (CS42L42_PAGE_15 + 0x01)
483 #define CS42L42_PLL_START_SHIFT 0
486 #define CS42L42_PLL_DIV_FRAC0 (CS42L42_PAGE_15 + 0x02)
487 #define CS42L42_PLL_DIV_FRAC_SHIFT 0
488 #define CS42L42_PLL_DIV_FRAC_MASK (0xff << CS42L42_PLL_DIV_FRAC_SHIFT)
490 #define CS42L42_PLL_DIV_FRAC1 (CS42L42_PAGE_15 + 0x03)
491 #define CS42L42_PLL_DIV_FRAC2 (CS42L42_PAGE_15 + 0x04)
493 #define CS42L42_PLL_DIV_INT (CS42L42_PAGE_15 + 0x05)
494 #define CS42L42_PLL_DIV_INT_SHIFT 0
495 #define CS42L42_PLL_DIV_INT_MASK (0xff << CS42L42_PLL_DIV_INT_SHIFT)
497 #define CS42L42_PLL_CTL3 (CS42L42_PAGE_15 + 0x08)
498 #define CS42L42_PLL_DIVOUT_SHIFT 0
499 #define CS42L42_PLL_DIVOUT_MASK (0xff << CS42L42_PLL_DIVOUT_SHIFT)
501 #define CS42L42_PLL_CAL_RATIO (CS42L42_PAGE_15 + 0x0A)
502 #define CS42L42_PLL_CAL_RATIO_SHIFT 0
503 #define CS42L42_PLL_CAL_RATIO_MASK (0xff << CS42L42_PLL_CAL_RATIO_SHIFT)
505 #define CS42L42_PLL_CTL4 (CS42L42_PAGE_15 + 0x1B)
506 #define CS42L42_PLL_MODE_SHIFT 0
509 /* Page 0x19 HP Load Detect Registers */
510 #define CS42L42_LOAD_DET_RCSTAT (CS42L42_PAGE_19 + 0x25)
511 #define CS42L42_RLA_STAT_SHIFT 0
513 #define CS42L42_RLA_STAT_15_OHM 0
515 #define CS42L42_LOAD_DET_DONE (CS42L42_PAGE_19 + 0x26)
516 #define CS42L42_HPLOAD_DET_DONE_SHIFT 0
519 #define CS42L42_LOAD_DET_EN (CS42L42_PAGE_19 + 0x27)
520 #define CS42L42_HP_LD_EN_SHIFT 0
523 /* Page 0x1B Headset Interface Registers */
524 #define CS42L42_HSBIAS_SC_AUTOCTL (CS42L42_PAGE_1B + 0x70)
525 #define CS42L42_HSBIAS_SENSE_TRIP_SHIFT 0
534 #define CS42L42_WAKE_CTL (CS42L42_PAGE_1B + 0x71)
535 #define CS42L42_WAKEB_CLEAR_SHIFT 0
544 #define CS42L42_ADC_DISABLE_MUTE (CS42L42_PAGE_1B + 0x72)
548 #define CS42L42_TIPSENSE_CTL (CS42L42_PAGE_1B + 0x73)
549 #define CS42L42_TIP_SENSE_DEBOUNCE_SHIFT 0
557 * NOTE: DETECT_MODE must be 0 while both ADC_PDN=1 and HP_PDN=1.
560 #define CS42L42_MISC_DET_CTL (CS42L42_PAGE_1B + 0x74)
561 #define CS42L42_PDN_MIC_LVL_DET_SHIFT 0
568 #define CS42L42_MIC_DET_CTL1 (CS42L42_PAGE_1B + 0x75)
569 #define CS42L42_HS_DET_LEVEL_SHIFT 0
570 #define CS42L42_HS_DET_LEVEL_MASK (0x3F << CS42L42_HS_DET_LEVEL_SHIFT)
576 #define CS42L42_MIC_DET_CTL2 (CS42L42_PAGE_1B + 0x76)
578 #define CS42L42_DEBOUNCE_TIME_MASK (0x07 << CS42L42_DEBOUNCE_TIME_SHIFT)
580 #define CS42L42_DET_STATUS1 (CS42L42_PAGE_1B + 0x77)
586 #define CS42L42_DET_STATUS2 (CS42L42_PAGE_1B + 0x78)
587 #define CS42L42_SHORT_TRUE_SHIFT 0
592 #define CS42L42_DET_INT1_MASK (CS42L42_PAGE_1B + 0x79)
603 #define CS42L42_DET_INT2_MASK (CS42L42_PAGE_1B + 0x7A)
604 #define CS42L42_M_SHORT_DET_SHIFT 0
620 /* Page 0x1C Headset Bias Registers */
621 #define CS42L42_HS_BIAS_CTL (CS42L42_PAGE_1C + 0x03)
622 #define CS42L42_HSBIAS_RAMP_SHIFT 0
629 /* Page 0x1D ADC Registers */
630 #define CS42L42_ADC_CTL (CS42L42_PAGE_1D + 0x01)
634 #define CS42L42_ADC_DIG_BOOST_SHIFT 0
636 #define CS42L42_ADC_VOLUME (CS42L42_PAGE_1D + 0x03)
637 #define CS42L42_ADC_VOL_SHIFT 0
639 #define CS42L42_ADC_WNF_HPF_CTL (CS42L42_PAGE_1D + 0x04)
643 #define CS42L42_ADC_HPF_EN_SHIFT 0
645 /* Page 0x1F DAC Registers */
646 #define CS42L42_DAC_CTL1 (CS42L42_PAGE_1F + 0x01)
648 #define CS42L42_DACA_INV_SHIFT 0
650 #define CS42L42_DAC_CTL2 (CS42L42_PAGE_1F + 0x06)
659 #define CS42L42_DAC_MON_EN_SHIFT 0
662 /* Page 0x20 HP CTL Registers */
663 #define CS42L42_HP_CTL (CS42L42_PAGE_20 + 0x01)
671 /* Page 0x21 Class H Registers */
672 #define CS42L42_CLASSH_CTL (CS42L42_PAGE_21 + 0x01)
674 /* Page 0x23 Mixer Volume Registers */
675 #define CS42L42_MIXER_CHA_VOL (CS42L42_PAGE_23 + 0x01)
676 #define CS42L42_MIXER_ADC_VOL (CS42L42_PAGE_23 + 0x02)
678 #define CS42L42_MIXER_CHB_VOL (CS42L42_PAGE_23 + 0x03)
679 #define CS42L42_MIXER_CH_VOL_SHIFT 0
680 #define CS42L42_MIXER_CH_VOL_MASK (0x3f << CS42L42_MIXER_CH_VOL_SHIFT)
682 /* Page 0x24 EQ Registers */
683 #define CS42L42_EQ_COEF_IN0 (CS42L42_PAGE_24 + 0x01)
684 #define CS42L42_EQ_COEF_IN1 (CS42L42_PAGE_24 + 0x02)
685 #define CS42L42_EQ_COEF_IN2 (CS42L42_PAGE_24 + 0x03)
686 #define CS42L42_EQ_COEF_IN3 (CS42L42_PAGE_24 + 0x04)
687 #define CS42L42_EQ_COEF_RW (CS42L42_PAGE_24 + 0x06)
688 #define CS42L42_EQ_COEF_OUT0 (CS42L42_PAGE_24 + 0x07)
689 #define CS42L42_EQ_COEF_OUT1 (CS42L42_PAGE_24 + 0x08)
690 #define CS42L42_EQ_COEF_OUT2 (CS42L42_PAGE_24 + 0x09)
691 #define CS42L42_EQ_COEF_OUT3 (CS42L42_PAGE_24 + 0x0A)
692 #define CS42L42_EQ_INIT_STAT (CS42L42_PAGE_24 + 0x0B)
693 #define CS42L42_EQ_START_FILT (CS42L42_PAGE_24 + 0x0C)
694 #define CS42L42_EQ_MUTE_CTL (CS42L42_PAGE_24 + 0x0E)
696 /* Page 0x25 Audio Port Registers */
697 #define CS42L42_SP_RX_CH_SEL (CS42L42_PAGE_25 + 0x01)
701 #define CS42L42_SP_RX_ISOC_CTL (CS42L42_PAGE_25 + 0x02)
708 #define CS42L42_SP_RX_ISOC_MODE_SHIFT 0
711 #define CS42L42_SP_RX_FS (CS42L42_PAGE_25 + 0x03)
712 #define CS42l42_SPDIF_CH_SEL (CS42L42_PAGE_25 + 0x04)
713 #define CS42L42_SP_TX_ISOC_CTL (CS42L42_PAGE_25 + 0x05)
714 #define CS42L42_SP_TX_FS (CS42L42_PAGE_25 + 0x06)
715 #define CS42L42_SPDIF_SW_CTL1 (CS42L42_PAGE_25 + 0x07)
717 /* Page 0x26 SRC Registers */
718 #define CS42L42_SRC_SDIN_FS (CS42L42_PAGE_26 + 0x01)
719 #define CS42L42_SRC_SDIN_FS_SHIFT 0
720 #define CS42L42_SRC_SDIN_FS_MASK (0x1f << CS42L42_SRC_SDIN_FS_SHIFT)
722 #define CS42L42_SRC_SDOUT_FS (CS42L42_PAGE_26 + 0x09)
724 /* Page 0x27 DMA */
725 #define CS42L42_SOFT_RESET_REBOOT (CS42L42_PAGE_27 + 0x01)
728 /* Page 0x28 S/PDIF Registers */
729 #define CS42L42_SPDIF_CTL1 (CS42L42_PAGE_28 + 0x01)
730 #define CS42L42_SPDIF_CTL2 (CS42L42_PAGE_28 + 0x02)
731 #define CS42L42_SPDIF_CTL3 (CS42L42_PAGE_28 + 0x03)
732 #define CS42L42_SPDIF_CTL4 (CS42L42_PAGE_28 + 0x04)
734 /* Page 0x29 Serial Port TX Registers */
735 #define CS42L42_ASP_TX_SZ_EN (CS42L42_PAGE_29 + 0x01)
736 #define CS42L42_ASP_TX_EN_SHIFT 0
737 #define CS42L42_ASP_TX_CH_EN (CS42L42_PAGE_29 + 0x02)
739 #define CS42L42_ASP_TX0_CH1_SHIFT 0
741 #define CS42L42_ASP_TX_CH_AP_RES (CS42L42_PAGE_29 + 0x03)
748 #define CS42L42_ASP_TX_CH1_RES_SHIFT 0
750 #define CS42L42_ASP_TX_CH1_BIT_MSB (CS42L42_PAGE_29 + 0x04)
751 #define CS42L42_ASP_TX_CH1_BIT_LSB (CS42L42_PAGE_29 + 0x05)
752 #define CS42L42_ASP_TX_HIZ_DLY_CFG (CS42L42_PAGE_29 + 0x06)
753 #define CS42L42_ASP_TX_CH2_BIT_MSB (CS42L42_PAGE_29 + 0x0A)
754 #define CS42L42_ASP_TX_CH2_BIT_LSB (CS42L42_PAGE_29 + 0x0B)
756 /* Page 0x2A Serial Port RX Registers */
757 #define CS42L42_ASP_RX_DAI0_EN (CS42L42_PAGE_2A + 0x01)
759 #define CS42L42_ASP_RX0_CH_EN_MASK (0xf << CS42L42_ASP_RX0_CH_EN_SHIFT)
765 #define CS42L42_ASP_RX_DAI0_CH1_AP_RES (CS42L42_PAGE_2A + 0x02)
766 #define CS42L42_ASP_RX_DAI0_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x03)
767 #define CS42L42_ASP_RX_DAI0_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x04)
768 #define CS42L42_ASP_RX_DAI0_CH2_AP_RES (CS42L42_PAGE_2A + 0x05)
769 #define CS42L42_ASP_RX_DAI0_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x06)
770 #define CS42L42_ASP_RX_DAI0_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x07)
771 #define CS42L42_ASP_RX_DAI0_CH3_AP_RES (CS42L42_PAGE_2A + 0x08)
772 #define CS42L42_ASP_RX_DAI0_CH3_BIT_MSB (CS42L42_PAGE_2A + 0x09)
773 #define CS42L42_ASP_RX_DAI0_CH3_BIT_LSB (CS42L42_PAGE_2A + 0x0A)
774 #define CS42L42_ASP_RX_DAI0_CH4_AP_RES (CS42L42_PAGE_2A + 0x0B)
775 #define CS42L42_ASP_RX_DAI0_CH4_BIT_MSB (CS42L42_PAGE_2A + 0x0C)
776 #define CS42L42_ASP_RX_DAI0_CH4_BIT_LSB (CS42L42_PAGE_2A + 0x0D)
777 #define CS42L42_ASP_RX_DAI1_CH1_AP_RES (CS42L42_PAGE_2A + 0x0E)
778 #define CS42L42_ASP_RX_DAI1_CH1_BIT_MSB (CS42L42_PAGE_2A + 0x0F)
779 #define CS42L42_ASP_RX_DAI1_CH1_BIT_LSB (CS42L42_PAGE_2A + 0x10)
780 #define CS42L42_ASP_RX_DAI1_CH2_AP_RES (CS42L42_PAGE_2A + 0x11)
781 #define CS42L42_ASP_RX_DAI1_CH2_BIT_MSB (CS42L42_PAGE_2A + 0x12)
782 #define CS42L42_ASP_RX_DAI1_CH2_BIT_LSB (CS42L42_PAGE_2A + 0x13)
786 #define CS42L42_ASP_RX_CH_AP_LOW 0
788 #define CS42L42_ASP_RX_CH_RES_SHIFT 0
792 #define CS42L42_ASP_RX_CH_BIT_ST_SHIFT 0
793 #define CS42L42_ASP_RX_CH_BIT_ST_MASK (0xff << CS42L42_ASP_RX_CH_BIT_ST_SHIFT)
795 /* Page 0x30 ID Registers */
796 #define CS42L42_SUB_REVID (CS42L42_PAGE_30 + 0x14)
797 #define CS42L42_MAX_REGISTER (CS42L42_PAGE_30 + 0x14)
800 #define CS42L42_FRAC0_VAL(val) ((val) & 0x0000ff)
801 #define CS42L42_FRAC1_VAL(val) (((val) & 0x00ff00) >> 8)
802 #define CS42L42_FRAC2_VAL(val) (((val) & 0xff0000) >> 16)