Lines Matching +full:tx1 +full:- +full:1
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
18 #define AK4114_REG_RCS1 0x07 /* receiver status 1 */
20 #define AK4114_REG_RXCSB1 0x09 /* RX channel status byte 1 */
25 #define AK4114_REG_TXCSB1 0x0e /* TX channel status byte 1 */
30 #define AK4114_REG_Pc1 0x13 /* burst preamble Pc byte 1 */
32 #define AK4114_REG_Pd1 0x15 /* burst preamble Pd byte 1 */
33 #define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */
34 #define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */
35 #define AK4114_REG_QSUB_INDEX 0x18 /* Q-subcode index */
36 #define AK4114_REG_QSUB_MINUTE 0x19 /* Q-subcode minute */
37 #define AK4114_REG_QSUB_SECOND 0x1a /* Q-subcode second */
38 #define AK4114_REG_QSUB_FRAME 0x1b /* Q-subcode frame */
39 #define AK4114_REG_QSUB_ZERO 0x1c /* Q-subcode zero */
40 #define AK4114_REG_QSUB_ABSMIN 0x1d /* Q-subcode absolute minute */
41 #define AK4114_REG_QSUB_ABSSEC 0x1e /* Q-subcode absolute second */
42 #define AK4114_REG_QSUB_ABSFRM 0x1f /* Q-subcode absolute frame */
45 #define AK4114_REG_RXCSB_SIZE ((AK4114_REG_RXCSB4-AK4114_REG_RXCSB0)+1)
46 #define AK4114_REG_TXCSB_SIZE ((AK4114_REG_TXCSB4-AK4114_REG_TXCSB0)+1)
47 #define AK4114_REG_QSUB_SIZE ((AK4114_REG_QSUB_ABSFRM-AK4114_REG_QSUB_ADDR)+1)
50 #define AK4114_CS12 (1<<7) /* Channel Status Select */
51 #define AK4114_BCU (1<<6) /* Block Start & C/U Output Mode */
52 #define AK4114_CM1 (1<<5) /* Master Clock Operation Select */
53 #define AK4114_CM0 (1<<4) /* Master Clock Operation Select */
54 #define AK4114_OCKS1 (1<<3) /* Master Clock Frequency Select */
55 #define AK4114_OCKS0 (1<<2) /* Master Clock Frequency Select */
56 #define AK4114_PWN (1<<1) /* 0 = power down, 1 = normal operation */
57 #define AK4114_RST (1<<0) /* 0 = reset & initialize (except this register), 1 = normal operation */
60 #define AK4114_MONO (1<<7) /* Double Sampling Frequency Mode: 0 = stereo, 1 = mono */
61 #define AK4114_DIF2 (1<<6) /* Audio Data Control */
62 #define AK4114_DIF1 (1<<5) /* Audio Data Control */
63 #define AK4114_DIF0 (1<<4) /* Audio Data Control */
64 #define AK4114_DIF_16R (0) /* STDO: 16-bit, right justified */
65 #define AK4114_DIF_18R (AK4114_DIF0) /* STDO: 18-bit, right justified */
66 #define AK4114_DIF_20R (AK4114_DIF1) /* STDO: 20-bit, right justified */
67 #define AK4114_DIF_24R (AK4114_DIF1|AK4114_DIF0) /* STDO: 24-bit, right justified */
68 #define AK4114_DIF_24L (AK4114_DIF2) /* STDO: 24-bit, left justified */
70 #define AK4114_DIF_I24L (AK4114_DIF2|AK4114_DIF1) /* STDO: 24-bit, left justified; LRCLK, BICK = I…
72 #define AK4114_DEAU (1<<3) /* Deemphasis Autodetect Enable (1 = enable) */
73 #define AK4114_DEM1 (1<<2) /* 32kHz-48kHz Deemphasis Control */
74 #define AK4114_DEM0 (1<<1) /* 32kHz-48kHz Deemphasis Control */
79 #define AK4114_DFS (1<<0) /* 96kHz Deemphasis Control */
82 #define AK4114_TX1E (1<<7) /* TX1 Output Enable (1 = enable) */
83 #define AK4114_OPS12 (1<<6) /* Output Data Selector for TX1 pin */
84 #define AK4114_OPS11 (1<<5) /* Output Data Selector for TX1 pin */
85 #define AK4114_OPS10 (1<<4) /* Output Data Selector for TX1 pin */
86 #define AK4114_TX0E (1<<3) /* TX0 Output Enable (1 = enable) */
87 #define AK4114_OPS02 (1<<2) /* Output Data Selector for TX0 pin */
88 #define AK4114_OPS01 (1<<1) /* Output Data Selector for TX0 pin */
89 #define AK4114_OPS00 (1<<0) /* Output Data Selector for TX0 pin */
92 #define AK4114_EFH1 (1<<7) /* Interrupt 0 pin Hold */
93 #define AK4114_EFH0 (1<<6) /* Interrupt 0 pin Hold */
98 #define AK4114_UDIT (1<<5) /* U-bit Control for DIT (0 = fixed '0', 1 = recovered) */
99 #define AK4114_TLR (1<<4) /* Double Sampling Frequency Select for DIT (0 = L channel, 1 = R channe…
100 #define AK4114_DIT (1<<3) /* TX1 out: 0 = Through Data (RX data), 1 = Transmit Data (DAUX data) */
101 #define AK4114_IPS2 (1<<2) /* Input Recovery Data Select */
102 #define AK4114_IPS1 (1<<1) /* Input Recovery Data Select */
103 #define AK4114_IPS0 (1<<0) /* Input Recovery Data Select */
107 #define AK4117_MQI (1<<7) /* mask enable for QINT bit */
108 #define AK4117_MAT (1<<6) /* mask enable for AUTO bit */
109 #define AK4117_MCI (1<<5) /* mask enable for CINT bit */
110 #define AK4117_MUL (1<<4) /* mask enable for UNLOCK bit */
111 #define AK4117_MDTS (1<<3) /* mask enable for DTSCD bit */
112 #define AK4117_MPE (1<<2) /* mask enable for PEM bit */
113 #define AK4117_MAN (1<<1) /* mask enable for AUDN bit */
114 #define AK4117_MPR (1<<0) /* mask enable for PAR bit */
117 #define AK4114_QINT (1<<7) /* Q-subcode buffer interrupt, 0 = no change, 1 = changed */
118 #define AK4114_AUTO (1<<6) /* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */
119 #define AK4114_CINT (1<<5) /* channel status buffer interrupt, 0 = no change, 1 = change */
120 #define AK4114_UNLCK (1<<4) /* PLL lock status, 0 = lock, 1 = unlock */
121 #define AK4114_DTSCD (1<<3) /* DTS-CD Detect, 0 = No detect, 1 = Detect */
122 #define AK4114_PEM (1<<2) /* Pre-emphasis Detect, 0 = OFF, 1 = ON */
123 #define AK4114_AUDION (1<<1) /* audio bit output, 0 = audio, 1 = non-audio */
124 #define AK4114_PAR (1<<0) /* parity error or biphase error status, 0 = no error, 1 = error */
127 #define AK4114_FS3 (1<<7) /* sampling frequency detection */
128 #define AK4114_FS2 (1<<6)
129 #define AK4114_FS1 (1<<5)
130 #define AK4114_FS0 (1<<4)
138 #define AK4114_V (1<<3) /* Validity of Channel Status, 0 = Valid, 1 = Invalid */
139 #define AK4114_QCRC (1<<1) /* CRC for Q-subcode, 0 = no error, 1 = error */
140 #define AK4114_CCRC (1<<0) /* CRC for channel status, 0 = no error, 1 = error */
143 #define AK4114_CHECK_NO_STAT (1<<0) /* no statistics */
144 #define AK4114_CHECK_NO_RATE (1<<1) /* no rate check */