Lines Matching +full:rx +full:- +full:input

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
13 #define AK4114_REG_IO0 0x02 /* input/output control */
14 #define AK4114_REG_IO1 0x03 /* input/output control */
19 #define AK4114_REG_RXCSB0 0x08 /* RX channel status byte 0 */
20 #define AK4114_REG_RXCSB1 0x09 /* RX channel status byte 1 */
21 #define AK4114_REG_RXCSB2 0x0a /* RX channel status byte 2 */
22 #define AK4114_REG_RXCSB3 0x0b /* RX channel status byte 3 */
23 #define AK4114_REG_RXCSB4 0x0c /* RX channel status byte 4 */
33 #define AK4114_REG_QSUB_ADDR 0x16 /* Q-subcode address + control */
34 #define AK4114_REG_QSUB_TRACK 0x17 /* Q-subcode track */
35 #define AK4114_REG_QSUB_INDEX 0x18 /* Q-subcode index */
36 #define AK4114_REG_QSUB_MINUTE 0x19 /* Q-subcode minute */
37 #define AK4114_REG_QSUB_SECOND 0x1a /* Q-subcode second */
38 #define AK4114_REG_QSUB_FRAME 0x1b /* Q-subcode frame */
39 #define AK4114_REG_QSUB_ZERO 0x1c /* Q-subcode zero */
40 #define AK4114_REG_QSUB_ABSMIN 0x1d /* Q-subcode absolute minute */
41 #define AK4114_REG_QSUB_ABSSEC 0x1e /* Q-subcode absolute second */
42 #define AK4114_REG_QSUB_ABSFRM 0x1f /* Q-subcode absolute frame */
45 #define AK4114_REG_RXCSB_SIZE ((AK4114_REG_RXCSB4-AK4114_REG_RXCSB0)+1)
46 #define AK4114_REG_TXCSB_SIZE ((AK4114_REG_TXCSB4-AK4114_REG_TXCSB0)+1)
47 #define AK4114_REG_QSUB_SIZE ((AK4114_REG_QSUB_ABSFRM-AK4114_REG_QSUB_ADDR)+1)
64 #define AK4114_DIF_16R (0) /* STDO: 16-bit, right justified */
65 #define AK4114_DIF_18R (AK4114_DIF0) /* STDO: 18-bit, right justified */
66 #define AK4114_DIF_20R (AK4114_DIF1) /* STDO: 20-bit, right justified */
67 #define AK4114_DIF_24R (AK4114_DIF1|AK4114_DIF0) /* STDO: 24-bit, right justified */
68 #define AK4114_DIF_24L (AK4114_DIF2) /* STDO: 24-bit, left justified */
70 …e AK4114_DIF_I24L (AK4114_DIF2|AK4114_DIF1) /* STDO: 24-bit, left justified; LRCLK, BICK = Input
71 #define AK4114_DIF_I24I2S (AK4114_DIF2|AK4114_DIF1|AK4114_DIF0) /* STDO: I2S; LRCLK, BICK = Input
73 #define AK4114_DEM1 (1<<2) /* 32kHz-48kHz Deemphasis Control */
74 #define AK4114_DEM0 (1<<1) /* 32kHz-48kHz Deemphasis Control */
98 #define AK4114_UDIT (1<<5) /* U-bit Control for DIT (0 = fixed '0', 1 = recovered) */
100 #define AK4114_DIT (1<<3) /* TX1 out: 0 = Through Data (RX data), 1 = Transmit Data (DAUX data) */
101 #define AK4114_IPS2 (1<<2) /* Input Recovery Data Select */
102 #define AK4114_IPS1 (1<<1) /* Input Recovery Data Select */
103 #define AK4114_IPS0 (1<<0) /* Input Recovery Data Select */
117 #define AK4114_QINT (1<<7) /* Q-subcode buffer interrupt, 0 = no change, 1 = changed */
118 #define AK4114_AUTO (1<<6) /* Non-PCM or DTS stream auto detection, 0 = no detect, 1 = detect */
121 #define AK4114_DTSCD (1<<3) /* DTS-CD Detect, 0 = No detect, 1 = Detect */
122 #define AK4114_PEM (1<<2) /* Pre-emphasis Detect, 0 = OFF, 1 = ON */
123 #define AK4114_AUDION (1<<1) /* audio bit output, 0 = audio, 1 = non-audio */
139 #define AK4114_QCRC (1<<1) /* CRC for Q-subcode, 0 = no error, 1 = error */