Lines Matching +full:assigned +full:- +full:resolution +full:- +full:bits
1 /* SPDX-License-Identifier: GPL-2.0+
33 /* range 0x28-0x3a - AUDIO AC'97 2.0 extensions */
44 /* range 0x3c-0x58 - MODEM */
59 /* range 0x5a-0x7b - Vendor Specific */
62 /* range 0x60-0x6f (page 1) - extended codec registers */
108 #define AC97_BC_16BIT_DAC 0x0000 /* 16-bit DAC resolution */
109 #define AC97_BC_18BIT_DAC 0x0040 /* 18-bit DAC resolution */
110 #define AC97_BC_20BIT_DAC 0x0080 /* 20-bit DAC resolution */
112 #define AC97_BC_16BIT_ADC 0x0000 /* 16-bit ADC resolution */
113 #define AC97_BC_18BIT_ADC 0x0100 /* 18-bit ADC resolution */
114 #define AC97_BC_20BIT_ADC 0x0200 /* 20-bit ADC resolution */
116 #define AC97_BC_3D_TECH_ID_MASK 0x7c00 /* Per-vendor ID of 3D enhancement */
123 /* powerdown bits */
132 #define AC97_PD_PR4 0x1000 /* Power down AC-Link */
157 #define AC97_EA_DRA 0x0002 /* Double-rate audio enable bit */
160 #define AC97_EA_SPSA_SLOT_MASK 0x0030 /* Mask for slot assignment bits */
162 #define AC97_EA_SPSA_3_4 0x0000 /* Slot assigned to 3 & 4 */
163 #define AC97_EA_SPSA_7_8 0x0010 /* Slot assigned to 7 & 8 */
164 #define AC97_EA_SPSA_6_9 0x0020 /* Slot assigned to 6 & 9 */
165 #define AC97_EA_SPSA_10_11 0x0030 /* Slot assigned to 10 & 11 */
184 #define AC97_SC_SPSR_MASK 0x3000 /* S/PDIF Sample Rate bits */
194 #define AC97_PAGE_VENDOR 0 /* Vendor-specific registers */
199 #define AC97_INT_CAUSE_GPIO 0x4000 /* GPIO bits changed (RO) */