Lines Matching +full:enable +full:- +full:soft +full:- +full:reset
1 /* SPDX-License-Identifier: GPL-2.0-only */
17 #define DDR3PHY_PIR_ITMSRST (1 << 4) /* Interface Timing Module Soft Reset */
19 #define DDR3PHY_PIR_DLLSRST (1 << 1) /* DLL Soft Rest */
30 #define DDR3PHY_ACDLLCR_DLLSRST (1 << 30) /* DLL Soft Reset */
44 #define DDR3PHY_ZQ0SR0_PDO_OFF (0) /* Pull-down output impedance select offset */
45 #define DDR3PHY_ZQ0SR0_PUO_OFF (5) /* Pull-up output impedance select offset */
46 #define DDR3PHY_ZQ0SR0_PDODT_OFF (10) /* Pull-down on-die termination impedance select offset */
47 #define DDR3PHY_ZQ0SRO_PUODT_OFF (15) /* Pull-up on-die termination impedance select offset */
55 #define UDDRC_STAT_SELFREF_TYPE_DIS (0x0 << 4) /* SDRAM is not in Self-refresh */
56 #define UDDRC_STAT_SELFREF_TYPE_PHY (0x1 << 4) /* SDRAM is in Self-refresh, which was caused by PH…
57 …_SELFREF_TYPE_SW (0x2 << 4) /* SDRAM is in Self-refresh, which was not caused solely under Automat…
58 …_STAT_SELFREF_TYPE_AUTO (0x3 << 4) /* SDRAM is in Self-refresh, which was caused by Automatic Self…
59 #define UDDRC_STAT_SELFREF_TYPE_MSK (0x3 << 4) /* Self-refresh type mask */
62 #define UDDRC_STAT_OPMODE_PWRDOWN (0x2 << 0) /* Power-down */
63 #define UDDRC_STAT_OPMODE_SELF_REFRESH (0x3 << 0) /* Self-refresh */
67 #define UDDRC_PWRCTL_SELFREF_EN (1 << 0) /* Automatic self-refresh */
68 #define UDDRC_PWRCTL_SELFREF_SW (1 << 5) /* Software self-refresh */
71 #define UDDRC_DFIMISC_DFI_INIT_COMPLETE_EN (1 << 0) /* PHY initialization complete enable signal */
73 #define UDDRC_SWCTRL (0x320) /* UDDRC Software Register Programming Control Enable */
74 #define UDDRC_SWCTRL_SW_DONE (1 << 0) /* Enable quasi-dynamic register programming outside reset …