soc/at91/at91sam9_sdramc.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  * arch/arm/mach-at91/include/mach/at91sam9_sdramc.h
8  * SDRAM Controllers (SDRAMC) - System peripherals registers.
35 #define		AT91_SDRAMC_NR		(3 << 2)		/* Number of Row Bits */
49 #define		AT91_SDRAMC_TWR		(0xf <<  8)		/* Write Recovery Delay */
50 #define		AT91_SDRAMC_TRC		(0xf << 12)		/* Row Cycle Delay */
51 #define		AT91_SDRAMC_TRP		(0xf << 16)		/* Row Precharge Delay */
52 #define		AT91_SDRAMC_TRCD	(0xf << 20)		/* Row to Column Delay */
53 #define		AT91_SDRAMC_TRAS	(0xf << 24)		/* Active to Precharge Delay */
54 #define		AT91_SDRAMC_TXSR	(0xf << 28)		/* Exit Self Refresh to Active Delay */
57 #define		AT91_SDRAMC_LPCB		(3 << 0)	/* Low-power Configurations */