soc/at91/at91sam9_ddrsdr.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
34 #define		AT91_DDRSDRC_NR		(3 << 2)		/* Number of Row Bits */
46 #define		AT91_DDRSDRC_OCD	(1 << 12)		/* Off-Chip Driver [SAM9 Only] */
51 #define		AT91_DDRSDRC_TRAS	(0xf <<  0)		/* Active to Precharge delay */
52 #define		AT91_DDRSDRC_TRCD	(0xf <<  4)		/* Row to Column delay */
53 #define		AT91_DDRSDRC_TWR	(0xf <<  8)		/* Write recovery delay */
54 #define		AT91_DDRSDRC_TRC	(0xf << 12)		/* Row cycle delay */
55 #define		AT91_DDRSDRC_TRP	(0xf << 16)		/* Row precharge delay */
57 #define		AT91_DDRSDRC_TWTR	(0x7 << 24)		/* Internal Write to Read delay */
58 #define		AT91_DDRSDRC_RED_WRRD	(0x1 << 27)		/* Reduce Write to Read Delay [SAM9 Only] */
59 #define		AT91_DDRSDRC_TMRD	(0xf << 28)		/* Load mode to active/refresh delay */
62 #define		AT91_DDRSDRC_TRFC	(0x1f << 0)		/* Row Cycle Delay */
63 #define		AT91_DDRSDRC_TXSNR	(0xff << 8)		/* Exit self-refresh to non-read */
64 #define		AT91_DDRSDRC_TXSRD	(0xff << 16)		/* Exit self-refresh to read */
65 #define		AT91_DDRSDRC_TXP	(0xf  << 24)		/* Exit power-down delay */
68 #define		AT91_DDRSDRC_TXARD	(0xf  << 0)		/* Exit active power down delay to read command in mode "F…
69 #define		AT91_DDRSDRC_TXARDS	(0xf  << 4)		/* Exit active power down delay to read command in mode "…
70 #define		AT91_DDRSDRC_TRPA	(0xf  << 8)		/* Row Precharge All delay */
71 #define		AT91_DDRSDRC_TRTP	(0x7  << 12)		/* Read to Precharge delay */
74 #define		AT91_DDRSDRC_LPCB	(3 << 0)		/* Low-power Configurations */
104 #define		AT91_DDRSDRC_MDINC	(1 << 0)		/* Master Delay increment */
105 #define		AT91_DDRSDRC_MDDEC	(1 << 1)		/* Master Delay decrement */
106 #define		AT91_DDRSDRC_MDOVF	(1 << 2)		/* Master Delay Overflow */
107 #define		AT91_DDRSDRC_MDVAL	(0xff <<  8)		/* Master Delay value */
112 #define AT91_DDRSDRC_DELAY(n)	(0x30 + (0x4 * (n)))	/* Delay I/O Register n */