Lines Matching +full:sense +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0
124 #define XTAL 0xC000 /* b15-14: Crystal selection */
132 #define LPSME 0x0100 /* b8: Low power sleep mode */
133 #define HSE 0x0080 /* b7: Hi-speed enable */
135 #define DRPD 0x0020 /* b5: D+/- pull down control */
140 #define OVCBIT 0x8000 /* b15-14: Over-current bit */
141 #define OVCMON 0xC000 /* b15-14: Over-current monitor */
143 #define IDMON 0x0004 /* b3: ID-pin monitor */
144 #define LNST 0x0003 /* b1-0: D+, D- line status */
146 #define FS_KSTS 0x0002 /* Full-Speed K State */
147 #define FS_JSTS 0x0001 /* Full-Speed J State */
148 #define LS_JSTS 0x0002 /* Low-Speed J State */
149 #define LS_KSTS 0x0001 /* Low-Speed K State */
156 #define RWUPE 0x0080 /* b7: Remote wakeup sense */
160 #define RHST 0x0007 /* b1-0: Reset handshake status */
162 #define HSMODE 0x0003 /* Hi-Speed mode */
163 #define FSMODE 0x0002 /* Full-Speed mode */
164 #define LSMODE 0x0001 /* Low-Speed mode */
167 /* Test Mode Register */
168 #define UTST 0x000F /* b3-0: Test select */
173 #define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
178 #define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
184 #define INTA 0x0001 /* b1: USB INT-pin active */
188 #define BURST 0x2000 /* b13: Burst mode */
190 #define DFORM 0x0380 /* b9-7: DMA mode select */
191 #define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
192 #define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
193 #define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
194 #define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
196 #define PKTM 0x0020 /* b5: Packet mode */
198 #define OBUS 0x0004 /* b2: OUTbus mode */
201 #define RCNT 0x8000 /* b15: Read count mode */
203 #define DCLRM 0x2000 /* b13: DMA buffer clear mode */
208 #define BIGEND 0x0100 /* b8: Big endian mode */
212 #define CURPIPE 0x000F /* b2-0: PIPE select */
218 #define DTLN 0x0FFF /* b11-0: FIFO received data length */
231 #define OVRCRE 0x8000 /* b15: Over-current interrupt */
233 #define DTCHE 0x1000 /* b12: Detach sense interrupt */
234 #define ATTCHE 0x0800 /* b11: Attach sense interrupt */
278 #define INTL 0x0020 /* b5: Interrupt sense select */
280 #define SOFMODE 0x000C /* b3-2: SOF pin select */
295 #define DVSQ 0x0070 /* b6-4: Device state */
305 #define DVSQS 0x0030 /* b5-4: Device state */
307 #define CTSQ 0x0007 /* b2-0: Control transfer stage */
317 #define OVRCR 0x8000 /* b15: Over-current interrupt */
319 #define DTCH 0x1000 /* b12: Detach sense interrupt */
320 #define ATTCH 0x0800 /* b11: Attach sense interrupt */
321 #define EOFERR 0x0040 /* b6: EOF-error interrupt */
328 #define FRNM 0x07FF /* b10-0: Frame number */
331 #define UFRNM 0x0007 /* b2-0: Micro frame number */
335 #define DEVSEL 0xF000 /* b15-14: Device address select */
336 #define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
341 #define CSCLR 0x2000 /* b13: complete-split status clear */
342 #define CSSTS 0x1000 /* b12: complete-split status */
350 #define PID 0x0003 /* b1-0: Response PID */
357 #define PIPENM 0x0007 /* b2-0: Pipe select */
360 #define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
364 #define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
365 #define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
366 #define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
369 #define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
372 #define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
373 #define BUFNMB 0x007F /* b6-0: Pipe buffer number */
378 #define MXPS 0x07FF /* b10-0: Maxpacket size */
381 #define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
382 #define IITV 0x0007 /* b2-0: Isochronous interval */
387 #define CSCLR 0x2000 /* b13: complete-split status clear */
388 #define CSSTS 0x1000 /* b12: complete-split status */
389 #define ATREPM 0x0400 /* b10: Auto repeat mode */
390 #define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
395 #define PID 0x0003 /* b1-0: Response PID */
402 #define TRNCNT 0xFFFF /* b15-0: Transaction counter */
432 #define SENDBUFM 0x1000 /* b12: Transmit Buffer Mode */
433 #define RCVENDM 0x0100 /* b8: Receive Data Transfer End Mode */
434 #define LBA_WAIT 0x0030 /* b5-4: Local Bus Access Wait */