Lines Matching +full:low +full:- +full:power
1 /* SPDX-License-Identifier: GPL-2.0 */
25 #define SSB_PCIE_DMA_L32 0x00000000U /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 …
33 #define SSB_MAX_NR_CORES ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
99 #define SSB_TMSLOW 0x0F98 /* SB Target State Low */
105 #define SSB_TMSLOW_PE 0x40000000 /* Power Management Enable */
108 #define SSB_TMSHIGH_SERR 0x00000001 /* S-error */
158 #define SSB_IDHIGH_RCLO 0x0000000F /* Revision Code (low part) */
168 * in two-byte quantities.
202 #define SSB_SPROM1_BINF_ANTBG 0x3000 /* Available B-PHY and G-PHY antennas */
204 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
217 #define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
218 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
219 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
225 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
226 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
228 #define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
230 #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
232 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
238 #define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
239 #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
240 #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
242 #define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
243 #define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
244 #define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
245 #define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
246 #define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
247 #define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
248 #define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
254 #define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
255 #define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
256 #define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
263 #define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
271 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
275 #define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
277 #define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
296 #define SSB_SPROM4_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
298 #define SSB_SPROM4_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
310 #define SSB_SPROM4_TXPID2G01 0x0062 /* TX Power Index 2GHz */
315 #define SSB_SPROM4_TXPID2G23 0x0064 /* TX Power Index 2GHz */
320 #define SSB_SPROM4_TXPID5G01 0x0066 /* TX Power Index 5GHz middle subband */
325 #define SSB_SPROM4_TXPID5G23 0x0068 /* TX Power Index 5GHz middle subband */
330 #define SSB_SPROM4_TXPID5GL01 0x006A /* TX Power Index 5GHz low subband */
335 #define SSB_SPROM4_TXPID5GL23 0x006C /* TX Power Index 5GHz low subband */
340 #define SSB_SPROM4_TXPID5GH01 0x006E /* TX Power Index 5GHz high subband */
345 #define SSB_SPROM4_TXPID5GH23 0x0070 /* TX Power Index 5GHz high subband */
351 /* There are 4 blocks with power info sharing the same layout */
357 #define SSB_SPROM4_2G_MAXP_ITSSI 0x00 /* 2 GHz ITSSI and 2 GHz Max Power */
361 #define SSB_SPROM4_2G_PA_0 0x02 /* 2 GHz power amp */
365 #define SSB_SPROM4_5G_MAXP_ITSSI 0x0A /* 5 GHz ITSSI and 5.3 GHz Max Power */
369 #define SSB_SPROM4_5GHL_MAXP 0x0C /* 5.2 GHz and 5.8 GHz Max Power */
373 #define SSB_SPROM4_5G_PA_0 0x0E /* 5.3 GHz power amp */
377 #define SSB_SPROM4_5GL_PA_0 0x16 /* 5.2 GHz power amp */
381 #define SSB_SPROM4_5GH_PA_0 0x1E /* 5.8 GHz power amp */
387 #define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
388 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
391 #define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
392 #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
404 #define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
406 #define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */
420 #define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
421 #define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
422 #define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
423 #define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
440 #define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
442 #define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
485 #define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
486 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
488 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
536 /* There are 4 blocks with power info sharing the same layout */
546 #define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
549 #define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
553 #define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
557 #define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
560 #define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
563 #define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
568 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
569 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
572 #define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
575 #define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
576 #define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
579 #define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
580 #define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
581 #define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
583 #define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
586 #define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
589 #define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
593 #define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
594 #define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
595 #define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
596 #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
597 #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
616 #define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
638 #define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
639 #define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
641 #define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
644 #define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
646 #define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
647 #define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
665 /* Address-Match values and masks (SSB_ADMATCHxxx) */