linux/ssb/ssb_driver_gige.h

14 #define SSB_GIGE_PCIIO			0x0000 /* PCI I/O Registers (1024 bytes) */
15 #define SSB_GIGE_RESERVED		0x0400 /* Reserved (1024 bytes) */
16 #define SSB_GIGE_PCICFG			0x0800 /* PCI config space (256 bytes) */
17 #define SSB_GIGE_SHIM_FLUSHSTAT		0x0C00 /* PCI to OCP: Flush status control (32bit) */
18 #define SSB_GIGE_SHIM_FLUSHRDA		0x0C04 /* PCI to OCP: Flush read address (32bit) */
19 #define SSB_GIGE_SHIM_FLUSHTO		0x0C08 /* PCI to OCP: Flush timeout counter (32bit) */
20 #define SSB_GIGE_SHIM_BARRIER		0x0C0C /* PCI to OCP: Barrier register (32bit) */
21 #define SSB_GIGE_SHIM_MAOCPSI		0x0C10 /* PCI to OCP: MaocpSI Control (32bit) */
22 #define SSB_GIGE_SHIM_SIOCPMA		0x0C14 /* PCI to OCP: SiocpMa Control (32bit) */
25 #define SSB_GIGE_TMSHIGH_RGMII		0x00010000 /* Have an RGMII PHY-bus */
27 #define SSB_GIGE_TMSLOW_TXBYPASS	0x00080000 /* TX bypass (no delay) */
28 #define SSB_GIGE_TMSLOW_RXBYPASS	0x00100000 /* RX bypass (no delay) */
29 #define SSB_GIGE_TMSLOW_DLLEN		0x01000000 /* Enable DLL controls */
32 #define SSB_GIGE_BFL_ROBOSWITCH		0x0010
69 	return (dev ? dev->has_rgmii : 0);  in ssb_gige_is_rgmii()
87 		return ((dev->dev->bus->chip_id == 0x4785) &&  in ssb_gige_one_dma_at_once()
97 		return (dev->dev->bus->chip_id == 0x4785);  in ssb_gige_must_flush_posted_writes()
109 	return 0;  in ssb_gige_get_macaddr()
154 	return 0;  in ssb_gige_init()