Lines Matching +full:0 +full:x1ff00000
8 * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
17 #define SSB_CHIPCO_CHIPID 0x0000
18 #define SSB_CHIPCO_IDMASK 0x0000FFFF
19 #define SSB_CHIPCO_REVMASK 0x000F0000
21 #define SSB_CHIPCO_PACKMASK 0x00F00000
23 #define SSB_CHIPCO_NRCORESMASK 0x0F000000
25 #define SSB_CHIPCO_CAP 0x0004 /* Capabilities */
26 #define SSB_CHIPCO_CAP_NRUART 0x00000003 /* # of UARTs */
27 #define SSB_CHIPCO_CAP_MIPSEB 0x00000004 /* MIPS in BigEndian Mode */
28 #define SSB_CHIPCO_CAP_UARTCLK 0x00000018 /* UART clock select */
29 #define SSB_CHIPCO_CAP_UARTCLK_INT 0x00000008 /* UARTs are driven by internal divided clock */
30 #define SSB_CHIPCO_CAP_UARTGPIO 0x00000020 /* UARTs on GPIO 15-12 */
31 #define SSB_CHIPCO_CAP_EXTBUS 0x000000C0 /* External buses present */
32 #define SSB_CHIPCO_CAP_FLASHT 0x00000700 /* Flash Type */
33 #define SSB_CHIPCO_FLASHT_NONE 0x00000000 /* No flash */
34 #define SSB_CHIPCO_FLASHT_STSER 0x00000100 /* ST serial flash */
35 #define SSB_CHIPCO_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
36 #define SSB_CHIPCO_FLASHT_PARA 0x00000700 /* Parallel flash */
37 #define SSB_CHIPCO_CAP_PLLT 0x00038000 /* PLL Type */
38 #define SSB_PLLTYPE_NONE 0x00000000
39 #define SSB_PLLTYPE_1 0x00010000 /* 48Mhz base, 3 dividers */
40 #define SSB_PLLTYPE_2 0x00020000 /* 48Mhz, 4 dividers */
41 #define SSB_PLLTYPE_3 0x00030000 /* 25Mhz, 2 dividers */
42 #define SSB_PLLTYPE_4 0x00008000 /* 48Mhz, 4 dividers */
43 #define SSB_PLLTYPE_5 0x00018000 /* 25Mhz, 4 dividers */
44 #define SSB_PLLTYPE_6 0x00028000 /* 100/200 or 120/240 only */
45 #define SSB_PLLTYPE_7 0x00038000 /* 25Mhz, 4 dividers */
46 #define SSB_CHIPCO_CAP_PCTL 0x00040000 /* Power Control */
47 #define SSB_CHIPCO_CAP_OTPS 0x00380000 /* OTP size */
50 #define SSB_CHIPCO_CAP_JTAGM 0x00400000 /* JTAG master present */
51 #define SSB_CHIPCO_CAP_BROM 0x00800000 /* Internal boot ROM active */
52 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
53 #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
54 #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
55 #define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */
56 #define SSB_CHIPCO_CORECTL 0x0008
57 #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
58 #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
59 #define SSB_CHIPCO_CORECTL_UARTCLKEN 0x00000008 /* UART clock enable (rev >= 21) */
60 #define SSB_CHIPCO_BIST 0x000C
61 #define SSB_CHIPCO_OTPS 0x0010 /* OTP status */
62 #define SSB_CHIPCO_OTPS_PROGFAIL 0x80000000
63 #define SSB_CHIPCO_OTPS_PROTECT 0x00000007
64 #define SSB_CHIPCO_OTPS_HW_PROTECT 0x00000001
65 #define SSB_CHIPCO_OTPS_SW_PROTECT 0x00000002
66 #define SSB_CHIPCO_OTPS_CID_PROTECT 0x00000004
67 #define SSB_CHIPCO_OTPC 0x0014 /* OTP control */
68 #define SSB_CHIPCO_OTPC_RECWAIT 0xFF000000
69 #define SSB_CHIPCO_OTPC_PROGWAIT 0x00FFFF00
71 #define SSB_CHIPCO_OTPC_MAXFAIL 0x00000038
72 #define SSB_CHIPCO_OTPC_VSEL 0x00000006
73 #define SSB_CHIPCO_OTPC_SELVL 0x00000001
74 #define SSB_CHIPCO_OTPP 0x0018 /* OTP prog */
75 #define SSB_CHIPCO_OTPP_COL 0x000000FF
76 #define SSB_CHIPCO_OTPP_ROW 0x0000FF00
78 #define SSB_CHIPCO_OTPP_READERR 0x10000000
79 #define SSB_CHIPCO_OTPP_VALUE 0x20000000
80 #define SSB_CHIPCO_OTPP_READ 0x40000000
81 #define SSB_CHIPCO_OTPP_START 0x80000000
82 #define SSB_CHIPCO_OTPP_BUSY 0x80000000
83 #define SSB_CHIPCO_IRQSTAT 0x0020
84 #define SSB_CHIPCO_IRQMASK 0x0024
85 #define SSB_CHIPCO_IRQ_GPIO 0x00000001 /* gpio intr */
86 #define SSB_CHIPCO_IRQ_EXT 0x00000002 /* ro: ext intr pin (corerev >= 3) */
87 #define SSB_CHIPCO_IRQ_WDRESET 0x80000000 /* watchdog reset occurred */
88 #define SSB_CHIPCO_CHIPCTL 0x0028 /* Rev >= 11 only */
89 #define SSB_CHIPCO_CHIPSTAT 0x002C /* Rev >= 11 only */
90 #define SSB_CHIPCO_JCMD 0x0030 /* Rev >= 10 only */
91 #define SSB_CHIPCO_JCMD_START 0x80000000
92 #define SSB_CHIPCO_JCMD_BUSY 0x80000000
93 #define SSB_CHIPCO_JCMD_PAUSE 0x40000000
94 #define SSB_CHIPCO_JCMD0_ACC_MASK 0x0000F000
95 #define SSB_CHIPCO_JCMD0_ACC_IRDR 0x00000000
96 #define SSB_CHIPCO_JCMD0_ACC_DR 0x00001000
97 #define SSB_CHIPCO_JCMD0_ACC_IR 0x00002000
98 #define SSB_CHIPCO_JCMD0_ACC_RESET 0x00003000
99 #define SSB_CHIPCO_JCMD0_ACC_IRPDR 0x00004000
100 #define SSB_CHIPCO_JCMD0_ACC_PDR 0x00005000
101 #define SSB_CHIPCO_JCMD0_IRW_MASK 0x00000F00
102 #define SSB_CHIPCO_JCMD_ACC_MASK 0x000F0000 /* Changes for corerev 11 */
103 #define SSB_CHIPCO_JCMD_ACC_IRDR 0x00000000
104 #define SSB_CHIPCO_JCMD_ACC_DR 0x00010000
105 #define SSB_CHIPCO_JCMD_ACC_IR 0x00020000
106 #define SSB_CHIPCO_JCMD_ACC_RESET 0x00030000
107 #define SSB_CHIPCO_JCMD_ACC_IRPDR 0x00040000
108 #define SSB_CHIPCO_JCMD_ACC_PDR 0x00050000
109 #define SSB_CHIPCO_JCMD_IRW_MASK 0x00001F00
111 #define SSB_CHIPCO_JCMD_DRW_MASK 0x0000003F
112 #define SSB_CHIPCO_JIR 0x0034 /* Rev >= 10 only */
113 #define SSB_CHIPCO_JDR 0x0038 /* Rev >= 10 only */
114 #define SSB_CHIPCO_JCTL 0x003C /* Rev >= 10 only */
118 #define SSB_CHIPCO_FLASHCTL 0x0040
119 #define SSB_CHIPCO_FLASHCTL_START 0x80000000
121 #define SSB_CHIPCO_FLASHADDR 0x0044
122 #define SSB_CHIPCO_FLASHDATA 0x0048
123 #define SSB_CHIPCO_BCAST_ADDR 0x0050
124 #define SSB_CHIPCO_BCAST_DATA 0x0054
125 #define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
126 #define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
127 #define SSB_CHIPCO_GPIOIN 0x0060
128 #define SSB_CHIPCO_GPIOOUT 0x0064
129 #define SSB_CHIPCO_GPIOOUTEN 0x0068
130 #define SSB_CHIPCO_GPIOCTL 0x006C
131 #define SSB_CHIPCO_GPIOPOL 0x0070
132 #define SSB_CHIPCO_GPIOIRQ 0x0074
133 #define SSB_CHIPCO_WATCHDOG 0x0080
134 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
135 #define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF
136 #define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0
137 #define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000
139 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
140 #define SSB_CHIPCO_CLOCK_N 0x0090
141 #define SSB_CHIPCO_CLOCK_SB 0x0094
142 #define SSB_CHIPCO_CLOCK_PCI 0x0098
143 #define SSB_CHIPCO_CLOCK_M2 0x009C
144 #define SSB_CHIPCO_CLOCK_MIPS 0x00A0
145 #define SSB_CHIPCO_CLKDIV 0x00A4 /* Rev >= 3 only */
146 #define SSB_CHIPCO_CLKDIV_SFLASH 0x0F000000
148 #define SSB_CHIPCO_CLKDIV_OTP 0x000F0000
150 #define SSB_CHIPCO_CLKDIV_JTAG 0x00000F00
152 #define SSB_CHIPCO_CLKDIV_UART 0x000000FF
153 #define SSB_CHIPCO_PLLONDELAY 0x00B0 /* Rev >= 4 only */
154 #define SSB_CHIPCO_FREFSELDELAY 0x00B4 /* Rev >= 4 only */
155 #define SSB_CHIPCO_SLOWCLKCTL 0x00B8 /* 6 <= Rev <= 9 only */
156 #define SSB_CHIPCO_SLOWCLKCTL_SRC 0x00000007 /* slow clock source mask */
157 #define SSB_CHIPCO_SLOWCLKCTL_SRC_LPO 0x00000000 /* source of slow clock is LPO */
158 #define SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL 0x00000001 /* source of slow clock is crystal */
159 #define SSB_CHIPCO_SLOECLKCTL_SRC_PCI 0x00000002 /* source of slow clock is PCI */
160 #define SSB_CHIPCO_SLOWCLKCTL_LPOFREQ 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
161 #define SSB_CHIPCO_SLOWCLKCTL_LPOPD 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enab…
162 #define SSB_CHIPCO_SLOWCLKCTL_FSLOW 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock,…
163 #define SSB_CHIPCO_SLOWCLKCTL_IPLL 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors …
164 #define SSB_CHIPCO_SLOWCLKCTL_ENXTAL 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't di…
165 #define SSB_CHIPCO_SLOWCLKCTL_XTALPU 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
166 #define SSB_CHIPCO_SLOWCLKCTL_CLKDIV 0xFFFF0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
168 #define SSB_CHIPCO_SYSCLKCTL 0x00C0 /* Rev >= 3 only */
169 #define SSB_CHIPCO_SYSCLKCTL_IDLPEN 0x00000001 /* ILPen: Enable Idle Low Power */
170 #define SSB_CHIPCO_SYSCLKCTL_ALPEN 0x00000002 /* ALPen: Enable Active Low Power */
171 #define SSB_CHIPCO_SYSCLKCTL_PLLEN 0x00000004 /* ForcePLLOn */
172 #define SSB_CHIPCO_SYSCLKCTL_FORCEALP 0x00000008 /* Force ALP (or HT if ALPen is not set */
173 #define SSB_CHIPCO_SYSCLKCTL_FORCEHT 0x00000010 /* Force HT */
174 #define SSB_CHIPCO_SYSCLKCTL_CLKDIV 0xFFFF0000 /* ClkDiv (ILP = 1/(4+divisor)) */
176 #define SSB_CHIPCO_CLKSTSTR 0x00C4 /* Rev >= 3 only */
177 #define SSB_CHIPCO_PCMCIA_CFG 0x0100
178 #define SSB_CHIPCO_PCMCIA_MEMWAIT 0x0104
179 #define SSB_CHIPCO_PCMCIA_ATTRWAIT 0x0108
180 #define SSB_CHIPCO_PCMCIA_IOWAIT 0x010C
181 #define SSB_CHIPCO_IDE_CFG 0x0110
182 #define SSB_CHIPCO_IDE_MEMWAIT 0x0114
183 #define SSB_CHIPCO_IDE_ATTRWAIT 0x0118
184 #define SSB_CHIPCO_IDE_IOWAIT 0x011C
185 #define SSB_CHIPCO_PROG_CFG 0x0120
186 #define SSB_CHIPCO_PROG_WAITCNT 0x0124
187 #define SSB_CHIPCO_FLASH_CFG 0x0128
188 #define SSB_CHIPCO_FLASH_WAITCNT 0x012C
189 #define SSB_CHIPCO_CLKCTLST 0x01E0 /* Clock control and status (rev >= 20) */
190 #define SSB_CHIPCO_CLKCTLST_FORCEALP 0x00000001 /* Force ALP request */
191 #define SSB_CHIPCO_CLKCTLST_FORCEHT 0x00000002 /* Force HT request */
192 #define SSB_CHIPCO_CLKCTLST_FORCEILP 0x00000004 /* Force ILP request */
193 #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
194 #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
195 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
196 #define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
197 #define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */
198 #define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
199 #define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
200 #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
201 #define SSB_CHIPCO_UART0_DATA 0x0300
202 #define SSB_CHIPCO_UART0_IMR 0x0304
203 #define SSB_CHIPCO_UART0_FCR 0x0308
204 #define SSB_CHIPCO_UART0_LCR 0x030C
205 #define SSB_CHIPCO_UART0_MCR 0x0310
206 #define SSB_CHIPCO_UART0_LSR 0x0314
207 #define SSB_CHIPCO_UART0_MSR 0x0318
208 #define SSB_CHIPCO_UART0_SCRATCH 0x031C
209 #define SSB_CHIPCO_UART1_DATA 0x0400
210 #define SSB_CHIPCO_UART1_IMR 0x0404
211 #define SSB_CHIPCO_UART1_FCR 0x0408
212 #define SSB_CHIPCO_UART1_LCR 0x040C
213 #define SSB_CHIPCO_UART1_MCR 0x0410
214 #define SSB_CHIPCO_UART1_LSR 0x0414
215 #define SSB_CHIPCO_UART1_MSR 0x0418
216 #define SSB_CHIPCO_UART1_SCRATCH 0x041C
218 #define SSB_CHIPCO_PMU_CTL 0x0600 /* PMU control */
219 #define SSB_CHIPCO_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
221 #define SSB_CHIPCO_PMU_CTL_PLL_UPD 0x00000400
222 #define SSB_CHIPCO_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
223 #define SSB_CHIPCO_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
224 #define SSB_CHIPCO_PMU_CTL_ALPREQEN 0x00000080 /* ALP req enable */
225 #define SSB_CHIPCO_PMU_CTL_XTALFREQ 0x0000007C /* Crystal freq */
227 #define SSB_CHIPCO_PMU_CTL_ILPDIVEN 0x00000002 /* ILP div enable */
228 #define SSB_CHIPCO_PMU_CTL_LPOSEL 0x00000001 /* LPO sel */
229 #define SSB_CHIPCO_PMU_CAP 0x0604 /* PMU capabilities */
230 #define SSB_CHIPCO_PMU_CAP_REVISION 0x000000FF /* Revision mask */
231 #define SSB_CHIPCO_PMU_STAT 0x0608 /* PMU status */
232 #define SSB_CHIPCO_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
233 #define SSB_CHIPCO_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
234 #define SSB_CHIPCO_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
235 #define SSB_CHIPCO_PMU_STAT_HAVEHT 0x00000004 /* HT available */
236 #define SSB_CHIPCO_PMU_STAT_RESINIT 0x00000003 /* Res init */
237 #define SSB_CHIPCO_PMU_RES_STAT 0x060C /* PMU res status */
238 #define SSB_CHIPCO_PMU_RES_PEND 0x0610 /* PMU res pending */
239 #define SSB_CHIPCO_PMU_TIMER 0x0614 /* PMU timer */
240 #define SSB_CHIPCO_PMU_MINRES_MSK 0x0618 /* PMU min res mask */
241 #define SSB_CHIPCO_PMU_MAXRES_MSK 0x061C /* PMU max res mask */
242 #define SSB_CHIPCO_PMU_RES_TABSEL 0x0620 /* PMU res table sel */
243 #define SSB_CHIPCO_PMU_RES_DEPMSK 0x0624 /* PMU res dep mask */
244 #define SSB_CHIPCO_PMU_RES_UPDNTM 0x0628 /* PMU res updown timer */
245 #define SSB_CHIPCO_PMU_RES_TIMER 0x062C /* PMU res timer */
246 #define SSB_CHIPCO_PMU_CLKSTRETCH 0x0630 /* PMU clockstretch */
247 #define SSB_CHIPCO_PMU_WATCHDOG 0x0634 /* PMU watchdog */
248 #define SSB_CHIPCO_PMU_RES_REQTS 0x0640 /* PMU res req timer sel */
249 #define SSB_CHIPCO_PMU_RES_REQT 0x0644 /* PMU res req timer */
250 #define SSB_CHIPCO_PMU_RES_REQM 0x0648 /* PMU res req mask */
251 #define SSB_CHIPCO_CHIPCTL_ADDR 0x0650
252 #define SSB_CHIPCO_CHIPCTL_DATA 0x0654
253 #define SSB_CHIPCO_REGCTL_ADDR 0x0658
254 #define SSB_CHIPCO_REGCTL_DATA 0x065C
255 #define SSB_CHIPCO_PLLCTL_ADDR 0x0660
256 #define SSB_CHIPCO_PLLCTL_DATA 0x0664
262 /* PMU rev 0 PLL registers */
263 #define SSB_PMU0_PLLCTL0 0
264 #define SSB_PMU0_PLLCTL0_PDIV_MSK 0x00000001
267 #define SSB_PMU0_PLLCTL1_WILD_IMSK 0xF0000000 /* Wild int mask (low nibble) */
269 #define SSB_PMU0_PLLCTL1_WILD_FMSK 0x0FFFFF00 /* Wild frac mask */
271 #define SSB_PMU0_PLLCTL1_STOPMOD 0x00000040 /* Stop mod */
273 #define SSB_PMU0_PLLCTL2_WILD_IMSKHI 0x0000000F /* Wild int mask (high nibble) */
274 #define SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT 0
277 #define SSB_PMU1_PLLCTL0 0
278 #define SSB_PMU1_PLLCTL0_P1DIV 0x00F00000 /* P1 div */
280 #define SSB_PMU1_PLLCTL0_P2DIV 0x0F000000 /* P2 div */
283 #define SSB_PMU1_PLLCTL1_M1DIV 0x000000FF /* M1 div */
284 #define SSB_PMU1_PLLCTL1_M1DIV_SHIFT 0
285 #define SSB_PMU1_PLLCTL1_M2DIV 0x0000FF00 /* M2 div */
287 #define SSB_PMU1_PLLCTL1_M3DIV 0x00FF0000 /* M3 div */
289 #define SSB_PMU1_PLLCTL1_M4DIV 0xFF000000 /* M4 div */
292 #define SSB_PMU1_PLLCTL2_M5DIV 0x000000FF /* M5 div */
293 #define SSB_PMU1_PLLCTL2_M5DIV_SHIFT 0
294 #define SSB_PMU1_PLLCTL2_M6DIV 0x0000FF00 /* M6 div */
296 #define SSB_PMU1_PLLCTL2_NDIVMODE 0x000E0000 /* NDIV mode */
298 #define SSB_PMU1_PLLCTL2_NDIVINT 0x1FF00000 /* NDIV int */
301 #define SSB_PMU1_PLLCTL3_NDIVFRAC 0x00FFFFFF /* NDIV frac */
302 #define SSB_PMU1_PLLCTL3_NDIVFRAC_SHIFT 0
305 #define SSB_PMU1_PLLCTL5_CLKDRV 0xFFFFFF00 /* clk drv */
309 #define SSB_PMURES_4312_SWITCHER_BURST 0
326 #define SSB_PMURES_4325_BUCK_BOOST_BURST 0
350 #define SSB_PMURES_4328_EXT_SWITCHER_PWM 0
372 #define SSB_PMURES_5354_EXT_SWITCHER_PWM 0
396 #define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */
397 #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
398 #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
402 #define SSB_CHIPCO_CHST_4325_SDIO_USB_MODE 0x00000004
404 #define SSB_CHIPCO_CHST_4325_RCAL_VALID 0x00000008
406 #define SSB_CHIPCO_CHST_4325_RCAL_VALUE 0x000001F0
408 #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
427 #define SSB_CHIPCO_CLK_N1 0x0000003F /* n1 control */
428 #define SSB_CHIPCO_CLK_N2 0x00003F00 /* n2 control */
430 #define SSB_CHIPCO_CLK_PLLC 0x000F0000 /* pll control */
434 #define SSB_CHIPCO_CLK_M1 0x0000003F /* m1 control */
435 #define SSB_CHIPCO_CLK_M2 0x00003F00 /* m2 control */
437 #define SSB_CHIPCO_CLK_M3 0x003F0000 /* m3 control */
439 #define SSB_CHIPCO_CLK_MC 0x1F000000 /* mux control */
443 #define SSB_CHIPCO_CLK_F6_2 0x02 /* A factor of 2 in */
444 #define SSB_CHIPCO_CLK_F6_3 0x03 /* 6-bit fields like */
445 #define SSB_CHIPCO_CLK_F6_4 0x05 /* N1, M1 or M3 */
446 #define SSB_CHIPCO_CLK_F6_5 0x09
447 #define SSB_CHIPCO_CLK_F6_6 0x11
448 #define SSB_CHIPCO_CLK_F6_7 0x21
452 #define SSB_CHIPCO_CLK_MC_BYPASS 0x08
453 #define SSB_CHIPCO_CLK_MC_M1 0x04
454 #define SSB_CHIPCO_CLK_MC_M1M2 0x02
455 #define SSB_CHIPCO_CLK_MC_M1M2M3 0x01
456 #define SSB_CHIPCO_CLK_MC_M1M3 0x11
468 #define SSB_CHIPCO_CLK_T6_M0 120000000 /* sb clock for m = 0 */
477 #define SSB_CHIPCO_CLK_5350_N 0x0311
478 #define SSB_CHIPCO_CLK_5350_M 0x04020009
483 #define SSB_CHIPCO_CFG_EN 0x0001 /* Enable */
484 #define SSB_CHIPCO_CFG_EXTM 0x000E /* Extif Mode */
485 #define SSB_CHIPCO_CFG_EXTM_ASYNC 0x0002 /* Async/Parallel flash */
486 #define SSB_CHIPCO_CFG_EXTM_SYNC 0x0004 /* Synchronous */
487 #define SSB_CHIPCO_CFG_EXTM_PCMCIA 0x0008 /* PCMCIA */
488 #define SSB_CHIPCO_CFG_EXTM_IDE 0x000A /* IDE */
489 #define SSB_CHIPCO_CFG_DS16 0x0010 /* Data size, 0=8bit, 1=16bit */
490 #define SSB_CHIPCO_CFG_CLKDIV 0x0060 /* Sync: Clock divisor */
491 #define SSB_CHIPCO_CFG_CLKEN 0x0080 /* Sync: Clock enable */
492 #define SSB_CHIPCO_CFG_BSTRO 0x0100 /* Sync: Size/Bytestrobe */
498 #define SSB_CHIPCO_FLASHCTL_ST_WREN 0x0006 /* Write Enable */
499 #define SSB_CHIPCO_FLASHCTL_ST_WRDIS 0x0004 /* Write Disable */
500 #define SSB_CHIPCO_FLASHCTL_ST_RDSR 0x0105 /* Read Status Register */
501 #define SSB_CHIPCO_FLASHCTL_ST_WRSR 0x0101 /* Write Status Register */
502 #define SSB_CHIPCO_FLASHCTL_ST_READ 0x0303 /* Read Data Bytes */
503 #define SSB_CHIPCO_FLASHCTL_ST_PP 0x0302 /* Page Program */
504 #define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */
505 #define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */
506 #define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */
507 #define SSB_CHIPCO_FLASHCTL_ST_RES 0x03AB /* Read Electronic Signature */
508 #define SSB_CHIPCO_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
509 #define SSB_CHIPCO_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
512 #define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */
513 #define SSB_CHIPCO_FLASHSTA_ST_WEL 0x02 /* Write Enable Latch */
514 #define SSB_CHIPCO_FLASHSTA_ST_BP 0x1C /* Block Protect */
516 #define SSB_CHIPCO_FLASHSTA_ST_SRWD 0x80 /* Status Register Write Disable */
519 #define SSB_CHIPCO_FLASHCTL_AT_READ 0x07E8
520 #define SSB_CHIPCO_FLASHCTL_AT_PAGE_READ 0x07D2
523 #define SSB_CHIPCO_FLASHCTL_AT_STATUS 0x01D7
524 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRITE 0x0384
525 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRITE 0x0387
526 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_ERASE_PRGM 0x0283 /* Erase program */
527 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_ERASE_PRGM 0x0286 /* Erase program */
528 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_PROGRAM 0x0288
529 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_PROGRAM 0x0289
530 #define SSB_CHIPCO_FLASHCTL_AT_PAGE_ERASE 0x0281
531 #define SSB_CHIPCO_FLASHCTL_AT_BLOCK_ERASE 0x0250
532 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_WRER_PRGM 0x0382 /* Write erase program */
533 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_WRER_PRGM 0x0385 /* Write erase program */
534 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_LOAD 0x0253
535 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_LOAD 0x0255
536 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_COMPARE 0x0260
537 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_COMPARE 0x0261
538 #define SSB_CHIPCO_FLASHCTL_AT_BUF1_REPROGRAM 0x0258
539 #define SSB_CHIPCO_FLASHCTL_AT_BUF2_REPROGRAM 0x0259
542 #define SSB_CHIPCO_FLASHSTA_AT_READY 0x80
543 #define SSB_CHIPCO_FLASHSTA_AT_MISMATCH 0x40
544 #define SSB_CHIPCO_FLASHSTA_AT_ID 0x38
557 #define SSB_CHIPCO_OTP_CIDBASE_OFF 0
566 #define SSB_CHIPCO_OTP_CID_OFF 0
572 #define SSB_CHIPCO_OTP_SIGNATURE 0x578A
573 #define SSB_CHIPCO_OTP_MAGIC 0x4E56
661 LDO_PAREF = 0,