1 /* SPDX-License-Identifier: GPL-2.0-or-later
36  * INTERFACES between SPI master-side drivers and SPI slave protocol handlers,
42  * struct spi_statistics - statistics for spi transfers
43  * @syncp:         seqcount to protect members in this struct for per-cpu update
44  *                 on 32-bit systems
46  * @messages:      number of spi-messages handled
62  *                 transfer bytes histogram
95 		u64_stats_update_begin(&__lstats->syncp);		\
96 		u64_stats_add(&__lstats->field, count);			\
97 		u64_stats_update_end(&__lstats->syncp);			\
106 		u64_stats_update_begin(&__lstats->syncp);		\
107 		u64_stats_inc(&__lstats->field);			\
108 		u64_stats_update_end(&__lstats->syncp);			\
113  * struct spi_delay - SPI delay information
131  * struct spi_device - Controller side proxy for an SPI slave device
136  *	The spi_transfer.speed_hz can override this for each transfer.
137  * @chip_select: Array of physical chipselect, spi->chipselect[i] gives
139  * @mode: The spi mode defines how data is clocked out and in.
143  *	each word in a transfer (by specifying SPI_LSB_FIRST).
144  * @bits_per_word: Data transfers involve one or more words; word sizes
145  *	like eight or 12 bits are common.  In-memory wordsizes are
149  *	The spi_transfer.bits_per_word can override this for each transfer.
154  * @controller_data: Board-specific definitions for controller, such as
166  *	words of a transfer
175  * A @spi_device is used to interchange data between an SPI slave
198 	 * only half-duplex, the wait state detection needs to be implemented
212 #define SPI_MODE_KERNEL_MASK	(~(BIT(29) - 1))
220 	struct spi_delay	word_delay; /* Inter-word delay */
239 	 *  - memory packing (12 bit samples into low bits, others zeroed)
240 	 *  - priority
241 	 *  - chipselect delays
242 	 *  - ...
258 	return (spi && get_device(&spi->dev)) ? spi : NULL;  in spi_dev_get()
264 		put_device(&spi->dev);  in spi_dev_put()
270 	return spi->controller_state;  in spi_get_ctldata()
275 	spi->controller_state = state;  in spi_set_ctldata()
278 /* Device driver data */
280 static inline void spi_set_drvdata(struct spi_device *spi, void *data)  in spi_set_drvdata()  argument
282 	dev_set_drvdata(&spi->dev, data);  in spi_set_drvdata()
287 	return dev_get_drvdata(&spi->dev);  in spi_get_drvdata()
292 	return spi->chip_select[idx];  in spi_get_chipselect()
297 	spi->chip_select[idx] = chipselect;  in spi_set_chipselect()
302 	return spi->cs_gpiod[idx];  in spi_get_csgpiod()
307 	spi->cs_gpiod[idx] = csgpiod;  in spi_set_csgpiod()
322  * struct spi_driver - Host side "protocol" driver
360  * spi_unregister_driver - reverse effect of spi_register_driver
367 		driver_unregister(&sdrv->driver);  in spi_unregister_driver()
377  * module_spi_driver() - Helper macro for registering a SPI driver
389  * struct spi_controller - interface to SPI master or slave controller
392  * @bus_num: board-specific (and often SOC-specific) identifier for a
403  *	supported. If set, the SPI core will reject any transfer with an
406  * @min_speed_hz: Lowest supported transfer speed
407  * @max_speed_hz: Highest supported transfer speed
411  * @devm_allocated: whether the allocation of this struct is devres-managed
412  * @max_transfer_size: function that returns the max transfer size for
429  * @transfer: adds a message to the controller's transfer queue.
430  * @cleanup: frees controller-specific state
440  * @cur_msg: the currently in-flight message
441  * @cur_msg_completion: a completion for the current in-flight message
448  * @fallback: fallback to PIO if DMA transfer return failure with
451  * @last_cs: the last chip_select that is recorded by set_cs, -1 on non chip
461  * @max_dma_len: Maximum length of a DMA transfer for the device.
463  *	so the subsystem requests the driver to prepare the transfer hardware
465  * @transfer_one_message: the subsystem calls the driver to transfer a single
478  * @prepare_message: set up the controller to transfer a single message,
481  * @transfer_one: transfer a single spi_transfer.
483  *                  - return 0 if the transfer is finished,
484  *                  - return 1 if the transfer is still in progress. When
485  *                    the driver is finished with this transfer it must
487  *                    can issue the next transfer. If the transfer fails, the
489  *                    spi_transfer->error first, before calling
501  * @target_abort: abort the ongoing transfer request on an SPI target controller
517  * @dummy_rx: dummy receive buffer for full-duplex devices
518  * @dummy_tx: dummy transmit buffer for full-duplex devices
523  *	time snapshot in @spi_transfer->ptp_sts as close as possible to the
524  *	moment in time when @spi_transfer->ptp_sts_word_pre and
525  *	@spi_transfer->ptp_sts_word_post were transmitted.
527  *	close to the driver hand-over as possible.
532  * @defer_optimize_message: set to true if controller cannot pre-optimize messages
543  * a queue of spi_message transactions, copying data between CPU memory and
554 	 * board-specific. Usually that simplifies to being SoC-specific.
556 	 * and one board's schematics might show it using SPI-2. Software
563 	 * might use board-specific GPIOs.
580 #define SPI_BPW_MASK(bits) BIT((bits) - 1)
581 #define SPI_BPW_RANGE_MASK(min, max) GENMASK((max) - 1, (min) - 1)
583 	/* Limits on transfer speed */
597 	 * The spi-controller has multi chip select capability and can
598 	 * assert/de-assert more than one chip select at once.
602 	/* Flag indicating if the allocation of this struct is devres-managed */
613 	 * On some hardware transfer / message size may be constrained
614 	 * the limit may depend on device transfer settings.
654 	 * + The transfer() method may not sleep; its main role is
656 	 * + For now there's no remove-from-queue operation, or
661 	 *   selecting a chip (for masters), then transferring data
671 	int			(*transfer)(struct spi_device *spi,  member
679 	 * exists and returns true then the transfer will be mapped
693 	 * controller transfer queueing mechanism. If these are used, the
694 	 * transfer() function above must NOT be specified by the driver.
735 			    struct spi_transfer *transfer);
739 	/* Optimized handlers for SPI memory-like operations. */
756 	/* Dummy data for full duplex devices */
779 	return dev_get_drvdata(&ctlr->dev);  in spi_controller_get_devdata()
783 					      void *data)  in spi_controller_set_devdata()  argument
785 	dev_set_drvdata(&ctlr->dev, data);  in spi_controller_set_devdata()
790 	if (!ctlr || !get_device(&ctlr->dev))  in spi_controller_get()
798 		put_device(&ctlr->dev);  in spi_controller_put()
803 	return IS_ENABLED(CONFIG_SPI_SLAVE) && ctlr->target;  in spi_controller_is_target()
815 /* Helper calls for driver to timestamp transfer */
912 	return ERR_PTR(-ENODEV);  in acpi_spi_device_alloc()
930  * struct spi_res - SPI resource management structure
933  * @data:    extra data allocated for the specific use-case
935  * This is based on ideas from devres, but focused on life-cycle
941 	unsigned long long      data[]; /* Guarantee ull alignment */  member
944 /*---------------------------------------------------------------------------*/
949  * Protocol drivers use a queue of spi_messages, each transferring data
952  * The spi_messages themselves consist of a series of read+write transfer
960  * well as the data buffers) for as long as the message is queued.
964  * struct spi_transfer - a read/write buffer pair
965  * @tx_buf: data to be written (DMA-safe memory), or NULL
966  * @rx_buf: data to be read (DMA-safe memory), or NULL
975  *      transfer. If 0 the default (from @spi_device) is used.
977  *      for this transfer. If 0 the default (from @spi_device) is used.
978  * @dummy_data: indicates transfer is dummy bytes transfer.
979  * @cs_off: performs the transfer with chipselect off.
980  * @cs_change: affects chipselect after this transfer completes
983  * @delay: delay to be introduced after this transfer before
985  *	the next transfer or completing this @spi_message.
988  * @effective_speed_hz: the effective SCK-speed that was used to
989  *      transfer this transfer. Set to 0 if the SPI bus driver does
998  *	snapshot for this transfer begins. Upon completing the SPI transfer,
1000  *	on the available snapshotting resolution (DMA transfer,
1006  *	@ptp_sts_word_post to the length of the transfer. This is done
1007  *	purposefully (instead of setting to spi_transfer->len - 1) to denote
1008  *	that a transfer-level snapshot taken from within the driver may still
1012  *	hardware has some sort of assist for retrieving exact transfer timing,
1019  * @timestamped: true if the transfer has been timestamped
1025  * the data being transferred; that may reduce overhead, when the
1029  * while filling @rx_buf.  If the receive buffer is NULL, the data
1035  * In-memory data values are always in native CPU byte order, translated
1036  * from the wire byte order (big-endian except with SPI_LSB_FIRST).  So
1040  * When the word size of the SPI transfer is not a power-of-two multiple
1041  * of eight bits, those in-memory words include extra bits.  In-memory
1042  * words are always seen by protocol drivers as right-justified, so the
1046  * it stays selected until after the last transfer in a message.  Drivers
1049  * (i) If the transfer isn't the last one in the message, this flag is
1055  * (ii) When the transfer is the last one in the message, the chip may
1056  * stay selected until the next transfer.  On multi-device SPI busses
1065  * When SPI can transfer in 1x,2x or 4x. It can get this transfer information
1066  * from device through @tx_nbits and @rx_nbits. In Bi-direction, these
1067  * two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x)
1068  * SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer.
1072  * Zero-initialize every field you don't set up explicitly, to
1104 #define	SPI_NBITS_SINGLE	0x01 /* 1-bit transfer */
1105 #define	SPI_NBITS_DUAL		0x02 /* 2-bit transfer */
1106 #define	SPI_NBITS_QUAD		0x04 /* 4-bit transfer */
1107 #define	SPI_NBITS_OCTAL	0x08 /* 8-bit transfer */
1125  * struct spi_message - one multi-segment SPI transaction
1126  * @transfers: list of transfer segments in this transaction
1128  * @pre_optimized: peripheral driver pre-optimized the message
1142  * A @spi_message is used to execute an atomic sequence of data transfers,
1146  * a single programmed DMA transfer.  On all systems, these messages are
1152  * Zero-initialize every field you don't set up explicitly, to
1171 	 * last transfer ... allowing things like "read 16 bit length L"
1175 	 * Some controller drivers (message-at-a-time queue processing)
1177 	 * others (with multi-message pipelines) could need a flag to
1207 	INIT_LIST_HEAD(&m->transfers);  in spi_message_init_no_memset()
1208 	INIT_LIST_HEAD(&m->resources);  in spi_message_init_no_memset()
1220 	list_add_tail(&t->transfer_list, &m->transfers);  in spi_message_add_tail()
1226 	list_del(&t->transfer_list);  in spi_transfer_del()
1232 	return spi_delay_exec(&t->delay, t);  in spi_transfer_delay_exec()
1236  * spi_message_init_with_transfers - Initialize spi_message and append transfers
1256  * It's fine to embed message and transaction structures in other data
1271 	spi_message_init_no_memset(&mwt->m);  in spi_message_alloc()
1273 		spi_message_add_tail(&mwt->t[i], &mwt->m);  in spi_message_alloc()
1275 	return &mwt->m;  in spi_message_alloc()
1295 	struct spi_controller *ctlr = spi->controller;  in spi_max_message_size()
1297 	if (!ctlr->max_message_size)  in spi_max_message_size()
1299 	return ctlr->max_message_size(spi);  in spi_max_message_size()
1305 	struct spi_controller *ctlr = spi->controller;  in spi_max_transfer_size()
1309 	if (ctlr->max_transfer_size)  in spi_max_transfer_size()
1310 		tr_max = ctlr->max_transfer_size(spi);  in spi_max_transfer_size()
1312 	/* Transfer size limit must not be greater than message size limit */  in spi_max_transfer_size()
1317  * spi_is_bpw_supported - Check if bits per word is supported
1328 	u32 bpw_mask = spi->controller->bits_per_word_mask;  in spi_is_bpw_supported()
1337  * spi_controller_xfer_timeout - Compute a suitable timeout value
1339  * @xfer: Transfer descriptor
1341  * Compute a relevant timeout value for the given transfer. We derive the time
1342  * that it would take on a single data line and take twice this amount of time
1345  * Returns: Transfer timeout value in milliseconds.
1350 	return max(xfer->len * 8 * 2 / (xfer->speed_hz / 1000), 500U);  in spi_controller_xfer_timeout()
1353 /*---------------------------------------------------------------------------*/
1355 /* SPI transfer replacement methods which make use of spi_res */
1362  * struct spi_replaced_transfers - structure describing the spi_transfer
1367  * @extradata:          pointer to some extra data if requested or NULL
1370  * @replaced_after:     the transfer after which the @replaced_transfers
1371  *                      are to get re-inserted
1373  * @inserted_transfers: array of spi_transfers of array-size @inserted,
1389 /*---------------------------------------------------------------------------*/
1391 /* SPI transfer transformation methods */
1400 /*---------------------------------------------------------------------------*/
1403  * All these synchronous SPI transfer routines are utilities layered
1404  * over the core async transfer primitive.  Here, "synchronous" means
1405  * they will sleep uninterruptibly until the async transfer completes.
1414  * spi_sync_transfer - synchronous SPI data transfer
1415  * @spi: device with which data will be exchanged
1420  * Does a synchronous SPI data transfer of the given spi_transfer array.
1438  * spi_write - SPI synchronous write
1439  * @spi: device to which data will be written
1440  * @buf: data buffer
1441  * @len: data buffer size
1461  * spi_read - SPI synchronous read
1462  * @spi: device from which data will be read
1463  * @buf: data buffer
1464  * @len: data buffer size
1483 /* This copies txbuf and rxbuf data; for small transfers only! */
1489  * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read
1490  * @spi: device with which data will be exchanged
1491  * @cmd: command to be written before data is read back
1511  * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read
1512  * @spi: device with which data will be exchanged
1513  * @cmd: command to be written before data is read back
1516  * The number is returned in wire-order, which is at least sometimes
1517  * big-endian.
1536  * spi_w8r16be - SPI synchronous 8 bit write followed by 16 bit big-endian read
1537  * @spi: device with which data will be exchanged
1538  * @cmd: command to be written before data is read back
1542  * convert the read 16 bit data word from big-endian to native endianness.
1562 /*---------------------------------------------------------------------------*/
1574  * support for non-static configurations too; enough to handle adding
1575  * parport adapters, or microcontrollers acting as USB-to-SPI bridges.
1579  * struct spi_board_info - board-specific template for a SPI device
1582  *	data stored there is driver-specific.
1588  *	from the chip datasheet and board-specific signal quality issues.
1600  * as the default transfer wordsize) is not included here.
1603  * be stored in tables of board-specific device descriptors, which are
1646 	 * ... may need additional spi_device chip config data here.
1649 	 *  - quirks like clock rate mattering when not selected
1695 	return list_is_last(&xfer->transfer_list, &ctlr->cur_msg->transfers);  in spi_transfer_is_last()