Lines Matching +full:0 +full:x0a0

19 #define HW_SSP_CTRL0				0x000
27 #define  BM_SSP_CTRL0_BUS_WIDTH			(0x3 << 22)
33 #define  BP_SSP_CTRL0_XFER_COUNT		0
34 #define  BM_SSP_CTRL0_XFER_COUNT		0xffff
35 #define HW_SSP_CMD0				0x010
41 #define  BM_SSP_CMD0_BLOCK_SIZE			(0xf << 16)
43 #define  BM_SSP_CMD0_BLOCK_COUNT		(0xff << 8)
44 #define  BP_SSP_CMD0_CMD			0
45 #define  BM_SSP_CMD0_CMD			0xff
46 #define HW_SSP_CMD1				0x020
47 #define HW_SSP_XFER_SIZE			0x030
48 #define HW_SSP_BLOCK_SIZE			0x040
50 #define  BM_SSP_BLOCK_SIZE_BLOCK_COUNT		(0xffffff << 4)
51 #define  BP_SSP_BLOCK_SIZE_BLOCK_SIZE		0
52 #define  BM_SSP_BLOCK_SIZE_BLOCK_SIZE		0xf
53 #define HW_SSP_TIMING(h)			(ssp_is_old(h) ? 0x050 : 0x070)
55 #define  BM_SSP_TIMING_TIMEOUT			(0xffff << 16)
57 #define  BM_SSP_TIMING_CLOCK_DIVIDE		(0xff << 8)
60 #define  BP_SSP_TIMING_CLOCK_RATE		0
61 #define  BM_SSP_TIMING_CLOCK_RATE		0xff
63 			(((v) << 0) & BM_SSP_TIMING_CLOCK_RATE)
64 #define HW_SSP_CTRL1(h)				(ssp_is_old(h) ? 0x060 : 0x080)
85 #define  BM_SSP_CTRL1_WORD_LENGTH		(0xf << 4)
88 #define  BV_SSP_CTRL1_WORD_LENGTH__FOUR_BITS	0x3
89 #define  BV_SSP_CTRL1_WORD_LENGTH__EIGHT_BITS	0x7
90 #define  BV_SSP_CTRL1_WORD_LENGTH__SIXTEEN_BITS	0xF
91 #define  BP_SSP_CTRL1_SSP_MODE			0
92 #define  BM_SSP_CTRL1_SSP_MODE			0xf
94 			(((v) << 0) & BM_SSP_CTRL1_SSP_MODE)
95 #define  BV_SSP_CTRL1_SSP_MODE__SPI		0x0
96 #define  BV_SSP_CTRL1_SSP_MODE__SSI		0x1
97 #define  BV_SSP_CTRL1_SSP_MODE__SD_MMC		0x3
98 #define  BV_SSP_CTRL1_SSP_MODE__MS		0x4
100 #define HW_SSP_DATA(h)				(ssp_is_old(h) ? 0x070 : 0x090)
102 #define HW_SSP_SDRESP0(h)			(ssp_is_old(h) ? 0x080 : 0x0a0)
103 #define HW_SSP_SDRESP1(h)			(ssp_is_old(h) ? 0x090 : 0x0b0)
104 #define HW_SSP_SDRESP2(h)			(ssp_is_old(h) ? 0x0a0 : 0x0c0)
105 #define HW_SSP_SDRESP3(h)			(ssp_is_old(h) ? 0x0b0 : 0x0d0)
106 #define HW_SSP_STATUS(h)			(ssp_is_old(h) ? 0x0c0 : 0x100)