Lines Matching +full:6 +full:- +full:bit
1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
36 #define SDW_DP0_INT_TEST_FAIL BIT(0)
37 #define SDW_DP0_INT_PORT_READY BIT(1)
38 #define SDW_DP0_INT_BRA_FAILURE BIT(2)
39 #define SDW_DP0_SDCA_CASCADE BIT(3)
40 /* BIT(4) not allocated in SoundWire specification 1.2 */
41 #define SDW_DP0_INT_IMPDEF1 BIT(5)
42 #define SDW_DP0_INT_IMPDEF2 BIT(6)
43 #define SDW_DP0_INT_IMPDEF3 BIT(7)
52 #define SDW_DP0_PORTCTRL_NXTINVBANK BIT(4)
53 #define SDW_DP0_PORTCTRL_BPT_PAYLD GENMASK(7, 6)
67 #define SDW_SCP_INT1_PARITY BIT(0)
68 #define SDW_SCP_INT1_BUS_CLASH BIT(1)
69 #define SDW_SCP_INT1_IMPL_DEF BIT(2)
70 #define SDW_SCP_INT1_SCP2_CASCADE BIT(7)
71 #define SDW_SCP_INT1_PORT0_3 GENMASK(6, 3)
74 #define SDW_SCP_INTSTAT2_SCP3_CASCADE BIT(7)
75 #define SDW_SCP_INTSTAT2_PORT4_10 GENMASK(6, 0)
87 #define SDW_SCP_CTRL_CLK_STP_NOW BIT(1)
88 #define SDW_SCP_CTRL_FORCE_RESET BIT(7)
91 #define SDW_SCP_STAT_CLK_STP_NF BIT(0)
92 #define SDW_SCP_STAT_HPHY_NOK BIT(5)
93 #define SDW_SCP_STAT_CURR_BANK BIT(6)
96 #define SDW_SCP_SYSTEMCTRL_CLK_STP_PREP BIT(0)
97 #define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE BIT(2)
98 #define SDW_SCP_SYSTEMCTRL_WAKE_UP_EN BIT(3)
99 #define SDW_SCP_SYSTEMCTRL_HIGH_PHY BIT(4)
102 #define SDW_SCP_SYSTEMCTRL_CLK_STP_MODE1 BIT(2)
134 #define SDW_SCP_SDCA_INT_SDCA_0 BIT(0)
135 #define SDW_SCP_SDCA_INT_SDCA_1 BIT(1)
136 #define SDW_SCP_SDCA_INT_SDCA_2 BIT(2)
137 #define SDW_SCP_SDCA_INT_SDCA_3 BIT(3)
138 #define SDW_SCP_SDCA_INT_SDCA_4 BIT(4)
139 #define SDW_SCP_SDCA_INT_SDCA_5 BIT(5)
140 #define SDW_SCP_SDCA_INT_SDCA_6 BIT(6)
141 #define SDW_SCP_SDCA_INT_SDCA_7 BIT(7)
144 #define SDW_SCP_SDCA_INT_SDCA_8 BIT(0)
145 #define SDW_SCP_SDCA_INT_SDCA_9 BIT(1)
146 #define SDW_SCP_SDCA_INT_SDCA_10 BIT(2)
147 #define SDW_SCP_SDCA_INT_SDCA_11 BIT(3)
148 #define SDW_SCP_SDCA_INT_SDCA_12 BIT(4)
149 #define SDW_SCP_SDCA_INT_SDCA_13 BIT(5)
150 #define SDW_SCP_SDCA_INT_SDCA_14 BIT(6)
151 #define SDW_SCP_SDCA_INT_SDCA_15 BIT(7)
154 #define SDW_SCP_SDCA_INT_SDCA_16 BIT(0)
155 #define SDW_SCP_SDCA_INT_SDCA_17 BIT(1)
156 #define SDW_SCP_SDCA_INT_SDCA_18 BIT(2)
157 #define SDW_SCP_SDCA_INT_SDCA_19 BIT(3)
158 #define SDW_SCP_SDCA_INT_SDCA_20 BIT(4)
159 #define SDW_SCP_SDCA_INT_SDCA_21 BIT(5)
160 #define SDW_SCP_SDCA_INT_SDCA_22 BIT(6)
161 #define SDW_SCP_SDCA_INT_SDCA_23 BIT(7)
164 #define SDW_SCP_SDCA_INT_SDCA_24 BIT(0)
165 #define SDW_SCP_SDCA_INT_SDCA_25 BIT(1)
166 #define SDW_SCP_SDCA_INT_SDCA_26 BIT(2)
167 #define SDW_SCP_SDCA_INT_SDCA_27 BIT(3)
168 #define SDW_SCP_SDCA_INT_SDCA_28 BIT(4)
169 #define SDW_SCP_SDCA_INT_SDCA_29 BIT(5)
170 #define SDW_SCP_SDCA_INT_SDCA_30 BIT(6)
171 /* BIT(7) not allocated in SoundWire 1.2 specification */
174 #define SDW_SCP_SDCA_INTMASK_SDCA_0 BIT(0)
175 #define SDW_SCP_SDCA_INTMASK_SDCA_1 BIT(1)
176 #define SDW_SCP_SDCA_INTMASK_SDCA_2 BIT(2)
177 #define SDW_SCP_SDCA_INTMASK_SDCA_3 BIT(3)
178 #define SDW_SCP_SDCA_INTMASK_SDCA_4 BIT(4)
179 #define SDW_SCP_SDCA_INTMASK_SDCA_5 BIT(5)
180 #define SDW_SCP_SDCA_INTMASK_SDCA_6 BIT(6)
181 #define SDW_SCP_SDCA_INTMASK_SDCA_7 BIT(7)
184 #define SDW_SCP_SDCA_INTMASK_SDCA_8 BIT(0)
185 #define SDW_SCP_SDCA_INTMASK_SDCA_9 BIT(1)
186 #define SDW_SCP_SDCA_INTMASK_SDCA_10 BIT(2)
187 #define SDW_SCP_SDCA_INTMASK_SDCA_11 BIT(3)
188 #define SDW_SCP_SDCA_INTMASK_SDCA_12 BIT(4)
189 #define SDW_SCP_SDCA_INTMASK_SDCA_13 BIT(5)
190 #define SDW_SCP_SDCA_INTMASK_SDCA_14 BIT(6)
191 #define SDW_SCP_SDCA_INTMASK_SDCA_15 BIT(7)
194 #define SDW_SCP_SDCA_INTMASK_SDCA_16 BIT(0)
195 #define SDW_SCP_SDCA_INTMASK_SDCA_17 BIT(1)
196 #define SDW_SCP_SDCA_INTMASK_SDCA_18 BIT(2)
197 #define SDW_SCP_SDCA_INTMASK_SDCA_19 BIT(3)
198 #define SDW_SCP_SDCA_INTMASK_SDCA_20 BIT(4)
199 #define SDW_SCP_SDCA_INTMASK_SDCA_21 BIT(5)
200 #define SDW_SCP_SDCA_INTMASK_SDCA_22 BIT(6)
201 #define SDW_SCP_SDCA_INTMASK_SDCA_23 BIT(7)
204 #define SDW_SCP_SDCA_INTMASK_SDCA_24 BIT(0)
205 #define SDW_SCP_SDCA_INTMASK_SDCA_25 BIT(1)
206 #define SDW_SCP_SDCA_INTMASK_SDCA_26 BIT(2)
207 #define SDW_SCP_SDCA_INTMASK_SDCA_27 BIT(3)
208 #define SDW_SCP_SDCA_INTMASK_SDCA_28 BIT(4)
209 #define SDW_SCP_SDCA_INTMASK_SDCA_29 BIT(5)
210 #define SDW_SCP_SDCA_INTMASK_SDCA_30 BIT(6)
211 /* BIT(7) not allocated in SoundWire 1.2 specification */
223 /* PHY registers - CTRL and STAT are the same address */
235 #define SDW_SCP_SLEW_TIME_CTRL GENMASK(7, 6)
245 #define SDW_DPN_INT_TEST_FAIL BIT(0)
246 #define SDW_DPN_INT_PORT_READY BIT(1)
247 #define SDW_DPN_INT_IMPDEF1 BIT(5)
248 #define SDW_DPN_INT_IMPDEF2 BIT(6)
249 #define SDW_DPN_INT_IMPDEF3 BIT(7)
258 #define SDW_DPN_PORTCTRL_NXTINVBANK BIT(4)
313 * v1.2 device - SDCA address mapping
321 * 21 Entity[6]
328 * 6:3 Control Selector[3:0]
332 #define SDW_SDCA_CTL(fun, ent, ctl, ch) (BIT(30) | \
341 #define SDW_SDCA_MBQ_CTL(reg) ((reg) | BIT(13))
342 #define SDW_SDCA_NEXT_CTL(reg) ((reg) | BIT(14))