linux/soundwire/sdw_intel.h

1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
2 /* Copyright(c) 2015-17 Intel Corporation. */
25 #define SDW_SHIM_LCAP_MLCS_MASK		BIT(8)
30 #define SDW_SHIM_LCTL_SPA		BIT(0)
32 #define SDW_SHIM_LCTL_CPA		BIT(8)
42 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24		(24000 / SDW_CADENCE_GSYNC_KHZ - 1)
43 #define SDW_SHIM_SYNC_SYNCPRD_VAL_24_576	(24576 / SDW_CADENCE_GSYNC_KHZ - 1)
44 #define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4		(38400 / SDW_CADENCE_GSYNC_KHZ - 1)
45 #define SDW_SHIM_SYNC_SYNCPRD_VAL_96		(96000 / SDW_CADENCE_GSYNC_KHZ - 1)
47 #define SDW_SHIM_SYNC_SYNCCPU		BIT(15)
49 #define SDW_SHIM_SYNC_CMDSYNC		BIT(16)
50 #define SDW_SHIM_SYNC_SYNCGO		BIT(24)
75 #define SDW_SHIM_PCMSYCM_DIR		BIT(15)
80 #define SDW_SHIM_IOCTL_MIF		BIT(0)
81 #define SDW_SHIM_IOCTL_CO		BIT(1)
82 #define SDW_SHIM_IOCTL_COE		BIT(2)
83 #define SDW_SHIM_IOCTL_DO		BIT(3)
84 #define SDW_SHIM_IOCTL_DOE		BIT(4)
85 #define SDW_SHIM_IOCTL_BKE		BIT(5)
86 #define SDW_SHIM_IOCTL_WPDD		BIT(6)
87 #define SDW_SHIM_IOCTL_CIBD		BIT(8)
88 #define SDW_SHIM_IOCTL_DIBD		BIT(9)
93 #define SDW_SHIM_WAKEEN_ENABLE		BIT(0)
98 #define SDW_SHIM_WAKESTS_STATUS		BIT(0)
103 #define SDW_SHIM_CTMCTL_DACTQE		BIT(0)
104 #define SDW_SHIM_CTMCTL_DODS		BIT(1)
116  * ACE2.x definitions for SHIM registers - only accessible when the
125 /* Read-only capabilities */
127 #define SDW_SHIM2_LECAP_HDS		BIT(0)		/* unset -> Host mode */
132 #define SDW_SHIM2_PCMSCAP_ISS		GENMASK(3, 0)	/* Input-only streams */
133 #define SDW_SHIM2_PCMSCAP_OSS		GENMASK(7, 4)	/* Output-only streams */
136 /* Read-only PCM Stream Channel Count, y variable is stream */
145 #define SDW_SHIM2_PCMSYCHM_DIR		BIT(15)		/* HDaudio stream direction */
147 /* SHIM2 vendor-specific registers */
149 #define SDW_SHIM2_INTEL_VS_LVSCTL_FCG	BIT(26)
151 #define SDW_SHIM2_INTEL_VS_LVSCTL_DCGD	BIT(30)
152 #define SDW_SHIM2_INTEL_VS_LVSCTL_ICGD	BIT(31)
161 #define SDW_SHIM2_INTEL_VS_WAKEEN_PWE	BIT(0)
164 #define SDW_SHIM2_INTEL_VS_WAKEEN_PWS	BIT(0)
167 #define SDW_SHIM2_INTEL_VS_IOCTL_MIF	BIT(0)
168 #define SDW_SHIM2_INTEL_VS_IOCTL_CO	BIT(1)
169 #define SDW_SHIM2_INTEL_VS_IOCTL_COE	BIT(2)
170 #define SDW_SHIM2_INTEL_VS_IOCTL_DO	BIT(3)
171 #define SDW_SHIM2_INTEL_VS_IOCTL_DOE	BIT(4)
172 #define SDW_SHIM2_INTEL_VS_IOCTL_BKE	BIT(5)
173 #define SDW_SHIM2_INTEL_VS_IOCTL_WPDD	BIT(6)
174 #define SDW_SHIM2_INTEL_VS_IOCTL_ODC	BIT(7)
175 #define SDW_SHIM2_INTEL_VS_IOCTL_CIBD	BIT(8)
176 #define SDW_SHIM2_INTEL_VS_IOCTL_DIBD	BIT(9)
177 #define SDW_SHIM2_INTEL_VS_IOCTL_HAMIFD	BIT(10)
180 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DACTQE	BIT(0)
181 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DODS		BIT(1)
182 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DODSE	BIT(2)
184 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DOAISE	BIT(5)
185 #define SDW_SHIM3_INTEL_VS_ACTMCTL_CLSS		BIT(6)
188 #define SDW_SHIM3_INTEL_VS_ACTMCTL_DOAISE2	BIT(14)
189 #define SDW_SHIM3_INTEL_VS_ACTMCTL_CLDE		BIT(15)
228  * struct sdw_intel_acpi_info - Soundwire Intel information found in ACPI tables
230  * @count: link count found with "sdw-master-count" or "sdw-manager-list" property
231  * @link_mask: bit-wise mask listing links enabled by BIOS menu
245 /* Intel clock-stop/pm_runtime quirk definitions */
252 #define SDW_INTEL_CLK_STOP_NOT_ALLOWED		BIT(0)
256  * reset and re-enumeration will be performed when the bus
258  * in-band wakes.
260 #define SDW_INTEL_CLK_STOP_TEARDOWN		BIT(1)
264  * (e.g. speaker amplifiers). The clock-stop mode is typically
265  * slightly higher power than when the IP is completely powered-off.
267 #define SDW_INTEL_CLK_STOP_WAKE_CAPABLE_ONLY	BIT(2)
270  * Require a bus reset (and complete re-enumeration) when exiting
277 #define SDW_INTEL_CLK_STOP_BUS_RESET		BIT(3)
282  * struct sdw_intel_ctx - context allocated by the controller
287  * @link_mask: bit-wise mask listing SoundWire links reported by the
291  * @ldev: information for each link (controller-specific and kept
317  * struct sdw_intel_res - Soundwire Intel global resource structure,
328  * @link_mask: bit-wise mask listing links selected by the DSP driver
330  * machine-specific quirks are handled in the DSP driver.
337  * @eml_lock: mutex protecting shared registers in the HDaudio multi-link
384 #define SDW_INTEL_QUIRK_MASK_BUS_DISABLE      BIT(1)
388 /* struct intel_sdw_hw_ops - SoundWire ops for Intel platforms.
398  * @link_power_up: power-up using chip-specific helpers
399  * @link_power_down: power-down with chip-specific helpers
401  * @shim_wake: enable/disable in-band wake management
404  * @sync_arm: helper for multi-link synchronization
405  * @sync_go_unlocked: helper for multi-link synchronization -
407  * @sync_go: helper for multi-link synchronization
408  * @sync_check_cmdsync_unlocked: helper for multi-link synchronization
409  * and bank switch - shim_lock is assumed to be locked at higher level
448  * and 6 system-unique Device Numbers for wake-capable devices.