linux/soundwire/sdw_intel.h

14 #define SDW_SHIM_BASE			0x2C000
15 #define SDW_ALH_BASE			0x2C800
16 #define SDW_SHIM_BASE_ACE		0x38000
17 #define SDW_ALH_BASE_ACE		0x24000
18 #define SDW_LINK_BASE			0x30000
19 #define SDW_LINK_SIZE			0x10000
23 #define SDW_SHIM_LCAP			0x0
24 #define SDW_SHIM_LCAP_LCOUNT_MASK	GENMASK(2, 0)
28 #define SDW_SHIM_LCTL			0x4
30 #define SDW_SHIM_LCTL_SPA		BIT(0)
31 #define SDW_SHIM_LCTL_SPA_MASK		GENMASK(3, 0)
35 #define SDW_SHIM_MLCS_XTAL_CLK		0x0
36 #define SDW_SHIM_MLCS_CARDINAL_CLK	0x1
37 #define SDW_SHIM_MLCS_AUDIO_PLL_CLK	0x2
40 #define SDW_SHIM_SYNC			0xC
46 #define SDW_SHIM_SYNC_SYNCPRD		GENMASK(14, 0)
53 #define SDW_SHIM_CTLSCAP(x)		(0x010 + 0x60 * (x))
54 #define SDW_SHIM_CTLS0CM(x)		(0x012 + 0x60 * (x))
55 #define SDW_SHIM_CTLS1CM(x)		(0x014 + 0x60 * (x))
56 #define SDW_SHIM_CTLS2CM(x)		(0x016 + 0x60 * (x))
57 #define SDW_SHIM_CTLS3CM(x)		(0x018 + 0x60 * (x))
60 #define SDW_SHIM_PCMSCAP(x)		(0x020 + 0x60 * (x))
62 #define SDW_SHIM_PCMSCAP_ISS		GENMASK(3, 0)
67 #define SDW_SHIM_PCMSYCHM(x, y)		(0x022 + (0x60 * (x)) + (0x2 * (y)))
70 #define SDW_SHIM_PCMSYCHC(x, y)		(0x042 + (0x60 * (x)) + (0x2 * (y)))
72 #define SDW_SHIM_PCMSYCM_LCHN		GENMASK(3, 0)
78 #define SDW_SHIM_IOCTL(x)		(0x06C + 0x60 * (x))
80 #define SDW_SHIM_IOCTL_MIF		BIT(0)
91 #define SDW_SHIM_WAKEEN			0x190
93 #define SDW_SHIM_WAKEEN_ENABLE		BIT(0)
96 #define SDW_SHIM_WAKESTS		0x192
98 #define SDW_SHIM_WAKESTS_STATUS		BIT(0)
101 #define SDW_SHIM_CTMCTL(x)		(0x06E + 0x60 * (x))
103 #define SDW_SHIM_CTMCTL_DACTQE		BIT(0)
108 #define SDW_ALH_STRMZCFG(x)		(0x000 + (0x4 * (x)))
111 #define SDW_ALH_STRMZCFG_DMAT_VAL	0x3
112 #define SDW_ALH_STRMZCFG_DMAT		GENMASK(7, 0)
120 #define SDW_SHIM2_GENERIC_BASE(x)	(0x00030000 + 0x8000 * (x))
121 #define SDW_IP_BASE(x)			(0x00030100 + 0x8000 * (x))
122 #define SDW_SHIM2_VS_BASE(x)		(0x00036000 + 0x8000 * (x))
126 #define SDW_SHIM2_LECAP			0x00
127 #define SDW_SHIM2_LECAP_HDS		BIT(0)		/* unset -> Host mode */
131 #define SDW_SHIM2_PCMSCAP		0x10
132 #define SDW_SHIM2_PCMSCAP_ISS		GENMASK(3, 0)	/* Input-only streams */
137 #define SDW_SHIM2_PCMSYCHC(y)		(0x14 + (0x4 * (y)))
138 #define SDW_SHIM2_PCMSYCHC_CS		GENMASK(3, 0)	/* Channels Supported */
141 #define SDW_SHIM2_PCMSYCHM(y)		(0x16 + (0x4 * (y)))
142 #define SDW_SHIM2_PCMSYCHM_LCHAN	GENMASK(3, 0)	/* Lowest channel used by the FIFO port */
148 #define SDW_SHIM2_INTEL_VS_LVSCTL	0x04
154 #define SDW_SHIM2_MLCS_XTAL_CLK		0x0
155 #define SDW_SHIM2_MLCS_CARDINAL_CLK	0x1
156 #define SDW_SHIM2_MLCS_AUDIO_PLL_CLK	0x2
157 #define SDW_SHIM2_MLCS_MCLK_INPUT_CLK	0x3
158 #define SDW_SHIM2_MLCS_WOV_RING_OSC_CLK 0x4
160 #define SDW_SHIM2_INTEL_VS_WAKEEN	0x08
161 #define SDW_SHIM2_INTEL_VS_WAKEEN_PWE	BIT(0)
163 #define SDW_SHIM2_INTEL_VS_WAKESTS	0x0A
164 #define SDW_SHIM2_INTEL_VS_WAKEEN_PWS	BIT(0)
166 #define SDW_SHIM2_INTEL_VS_IOCTL	0x0C
167 #define SDW_SHIM2_INTEL_VS_IOCTL_MIF	BIT(0)
179 #define SDW_SHIM2_INTEL_VS_ACTMCTL	0x0E
180 #define SDW_SHIM2_INTEL_VS_ACTMCTL_DACTQE	BIT(0)
252 #define SDW_INTEL_CLK_STOP_NOT_ALLOWED		BIT(0)