Lines Matching +full:0 +full:x3c8
5 #define MT8365_INFRA_TOPAXI_PROTECTEN_STA1 0x228
6 #define MT8365_INFRA_TOPAXI_PROTECTEN_SET 0x2a0
7 #define MT8365_INFRA_TOPAXI_PROTECTEN_CLR 0x2a4
17 #define MT8365_INFRA_TOPAXI_PROTECTEN_1_STA1 0x258
18 #define MT8365_INFRA_TOPAXI_PROTECTEN_1_SET 0x2a8
19 #define MT8365_INFRA_TOPAXI_PROTECTEN_1_CLR 0x2ac
33 #define MT8365_INFRA_NAO_TOPAXI_SI0_STA 0x0
35 #define MT8365_INFRA_NAO_TOPAXI_SI2_STA 0x28
37 #define MT8365_INFRA_TOPAXI_SI0_CTL 0x200
39 #define MT8365_INFRA_TOPAXI_SI2_CTL 0x234
42 #define MT8365_SMI_COMMON_CLAMP_EN 0x3c0
43 #define MT8365_SMI_COMMON_CLAMP_EN_SET 0x3c4
44 #define MT8365_SMI_COMMON_CLAMP_EN_CLR 0x3c8
46 #define MT8195_TOP_AXI_PROT_EN_STA1 0x228
47 #define MT8195_TOP_AXI_PROT_EN_1_STA1 0x258
48 #define MT8195_TOP_AXI_PROT_EN_SET 0x2a0
49 #define MT8195_TOP_AXI_PROT_EN_CLR 0x2a4
50 #define MT8195_TOP_AXI_PROT_EN_1_SET 0x2a8
51 #define MT8195_TOP_AXI_PROT_EN_1_CLR 0x2ac
52 #define MT8195_TOP_AXI_PROT_EN_MM_SET 0x2d4
53 #define MT8195_TOP_AXI_PROT_EN_MM_CLR 0x2d8
54 #define MT8195_TOP_AXI_PROT_EN_MM_STA1 0x2ec
55 #define MT8195_TOP_AXI_PROT_EN_2_SET 0x714
56 #define MT8195_TOP_AXI_PROT_EN_2_CLR 0x718
57 #define MT8195_TOP_AXI_PROT_EN_2_STA1 0x724
58 #define MT8195_TOP_AXI_PROT_EN_VDNR_SET 0xb84
59 #define MT8195_TOP_AXI_PROT_EN_VDNR_CLR 0xb88
60 #define MT8195_TOP_AXI_PROT_EN_VDNR_STA1 0xb90
61 #define MT8195_TOP_AXI_PROT_EN_VDNR_1_SET 0xba4
62 #define MT8195_TOP_AXI_PROT_EN_VDNR_1_CLR 0xba8
63 #define MT8195_TOP_AXI_PROT_EN_VDNR_1_STA1 0xbb0
64 #define MT8195_TOP_AXI_PROT_EN_VDNR_2_SET 0xbb8
65 #define MT8195_TOP_AXI_PROT_EN_VDNR_2_CLR 0xbbc
66 #define MT8195_TOP_AXI_PROT_EN_VDNR_2_STA1 0xbc4
67 #define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xbcc
68 #define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xbd0
69 #define MT8195_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA1 0xbd8
70 #define MT8195_TOP_AXI_PROT_EN_MM_2_SET 0xdcc
71 #define MT8195_TOP_AXI_PROT_EN_MM_2_CLR 0xdd0
72 #define MT8195_TOP_AXI_PROT_EN_MM_2_STA1 0xdd8
81 #define MT8195_TOP_AXI_PROT_EN_2_CAM BIT(0)
86 #define MT8195_TOP_AXI_PROT_EN_MM_CAM (BIT(0) | BIT(2) | BIT(4))
104 #define MT8195_TOP_AXI_PROT_EN_MM_2_VPPSYS0_2ND (GENMASK(1, 0) | BIT(4) | BIT(11))
128 #define MT8192_TOP_AXI_PROT_EN_STA1 0x228
129 #define MT8192_TOP_AXI_PROT_EN_1_STA1 0x258
130 #define MT8192_TOP_AXI_PROT_EN_SET 0x2a0
131 #define MT8192_TOP_AXI_PROT_EN_CLR 0x2a4
132 #define MT8192_TOP_AXI_PROT_EN_1_SET 0x2a8
133 #define MT8192_TOP_AXI_PROT_EN_1_CLR 0x2ac
134 #define MT8192_TOP_AXI_PROT_EN_MM_SET 0x2d4
135 #define MT8192_TOP_AXI_PROT_EN_MM_CLR 0x2d8
136 #define MT8192_TOP_AXI_PROT_EN_MM_STA1 0x2ec
137 #define MT8192_TOP_AXI_PROT_EN_2_SET 0x714
138 #define MT8192_TOP_AXI_PROT_EN_2_CLR 0x718
139 #define MT8192_TOP_AXI_PROT_EN_2_STA1 0x724
140 #define MT8192_TOP_AXI_PROT_EN_VDNR_SET 0xb84
141 #define MT8192_TOP_AXI_PROT_EN_VDNR_CLR 0xb88
142 #define MT8192_TOP_AXI_PROT_EN_VDNR_STA1 0xb90
143 #define MT8192_TOP_AXI_PROT_EN_MM_2_SET 0xdcc
144 #define MT8192_TOP_AXI_PROT_EN_MM_2_CLR 0xdd0
145 #define MT8192_TOP_AXI_PROT_EN_MM_2_STA1 0xdd8
154 #define MT8192_TOP_AXI_PROT_EN_2_CAM BIT(0)
159 #define MT8192_TOP_AXI_PROT_EN_MM_CAM (BIT(0) | BIT(2))
160 #define MT8192_TOP_AXI_PROT_EN_MM_DISP (BIT(0) | BIT(2) | \
184 #define MT8188_TOP_AXI_PROT_EN_SET 0x2A0
185 #define MT8188_TOP_AXI_PROT_EN_CLR 0x2A4
186 #define MT8188_TOP_AXI_PROT_EN_STA 0x228
187 #define MT8188_TOP_AXI_PROT_EN_1_SET 0x2A8
188 #define MT8188_TOP_AXI_PROT_EN_1_CLR 0x2AC
189 #define MT8188_TOP_AXI_PROT_EN_1_STA 0x258
190 #define MT8188_TOP_AXI_PROT_EN_2_SET 0x714
191 #define MT8188_TOP_AXI_PROT_EN_2_CLR 0x718
192 #define MT8188_TOP_AXI_PROT_EN_2_STA 0x724
194 #define MT8188_TOP_AXI_PROT_EN_MM_SET 0x2D4
195 #define MT8188_TOP_AXI_PROT_EN_MM_CLR 0x2D8
196 #define MT8188_TOP_AXI_PROT_EN_MM_STA 0x2EC
197 #define MT8188_TOP_AXI_PROT_EN_MM_2_SET 0xDCC
198 #define MT8188_TOP_AXI_PROT_EN_MM_2_CLR 0xDD0
199 #define MT8188_TOP_AXI_PROT_EN_MM_2_STA 0xDD8
201 #define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET 0xB84
202 #define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR 0xB88
203 #define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA 0xB90
204 #define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET 0xBCC
205 #define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR 0xBD0
206 #define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA 0xBD8
263 #define MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2 BIT(0)
272 #define MT8188_SMI_COMMON_CLAMP_EN_STA 0x3C0
273 #define MT8188_SMI_COMMON_CLAMP_EN_SET 0x3C4
274 #define MT8188_SMI_COMMON_CLAMP_EN_CLR 0x3C8
278 #define MT8188_SMI_COMMON_SMI_CLAMP_IPE_TO_VPP1 BIT(0)
283 #define MT8188_SMI_LARB10_RESET_ADDR 0xC
284 #define MT8188_SMI_LARB11A_RESET_ADDR 0xC
285 #define MT8188_SMI_LARB11C_RESET_ADDR 0xC
286 #define MT8188_SMI_LARB12_RESET_ADDR 0xC
287 #define MT8188_SMI_LARB11B_RESET_ADDR 0xC
288 #define MT8188_SMI_LARB15_RESET_ADDR 0xC
289 #define MT8188_SMI_LARB16B_RESET_ADDR 0xA0
290 #define MT8188_SMI_LARB17B_RESET_ADDR 0xA0
291 #define MT8188_SMI_LARB16A_RESET_ADDR 0xA0
292 #define MT8188_SMI_LARB17A_RESET_ADDR 0xA0
294 #define MT8188_SMI_LARB10_RESET BIT(0)
295 #define MT8188_SMI_LARB11A_RESET BIT(0)
296 #define MT8188_SMI_LARB11C_RESET BIT(0)
298 #define MT8188_SMI_LARB11B_RESET BIT(0)
299 #define MT8188_SMI_LARB15_RESET BIT(0)
305 #define MT8186_TOP_AXI_PROT_EN_SET (0x2A0)
306 #define MT8186_TOP_AXI_PROT_EN_CLR (0x2A4)
307 #define MT8186_TOP_AXI_PROT_EN_STA (0x228)
308 #define MT8186_TOP_AXI_PROT_EN_1_SET (0x2A8)
309 #define MT8186_TOP_AXI_PROT_EN_1_CLR (0x2AC)
310 #define MT8186_TOP_AXI_PROT_EN_1_STA (0x258)
311 #define MT8186_TOP_AXI_PROT_EN_2_SET (0x2B0)
312 #define MT8186_TOP_AXI_PROT_EN_2_CLR (0x2B4)
313 #define MT8186_TOP_AXI_PROT_EN_2_STA (0x26C)
314 #define MT8186_TOP_AXI_PROT_EN_3_SET (0x2B8)
315 #define MT8186_TOP_AXI_PROT_EN_3_CLR (0x2BC)
316 #define MT8186_TOP_AXI_PROT_EN_3_STA (0x2C8)
351 #define MT8186_TOP_AXI_PROT_EN_3_ADSP_TOP_STEP2 (GENMASK(1, 0))
353 #define MT8183_TOP_AXI_PROT_EN_STA1 0x228
354 #define MT8183_TOP_AXI_PROT_EN_STA1_1 0x258
355 #define MT8183_TOP_AXI_PROT_EN_SET 0x2a0
356 #define MT8183_TOP_AXI_PROT_EN_CLR 0x2a4
357 #define MT8183_TOP_AXI_PROT_EN_1_SET 0x2a8
358 #define MT8183_TOP_AXI_PROT_EN_1_CLR 0x2ac
359 #define MT8183_TOP_AXI_PROT_EN_MCU_SET 0x2c4
360 #define MT8183_TOP_AXI_PROT_EN_MCU_CLR 0x2c8
361 #define MT8183_TOP_AXI_PROT_EN_MCU_STA1 0x2e4
362 #define MT8183_TOP_AXI_PROT_EN_MM_SET 0x2d4
363 #define MT8183_TOP_AXI_PROT_EN_MM_CLR 0x2d8
364 #define MT8183_TOP_AXI_PROT_EN_MM_STA1 0x2ec
381 #define MT8183_TOP_AXI_PROT_EN_MCU_VPU_CORE0_2ND (BIT(0) | BIT(2) | \
388 #define MT8183_SMI_COMMON_CLAMP_EN 0x3c0
389 #define MT8183_SMI_COMMON_CLAMP_EN_SET 0x3c4
390 #define MT8183_SMI_COMMON_CLAMP_EN_CLR 0x3c8
392 #define MT8183_SMI_COMMON_SMI_CLAMP_DISP GENMASK(7, 0)
399 #define MT8173_TOP_AXI_PROT_EN_MCI_M2 BIT(0)
437 #define INFRA_TOPAXI_PROTECTEN 0x0220
438 #define INFRA_TOPAXI_PROTECTSTA1 0x0228
439 #define INFRA_TOPAXI_PROTECTEN_SET 0x0260
440 #define INFRA_TOPAXI_PROTECTEN_CLR 0x0264
442 #define MT8192_INFRA_CTRL 0x290
445 #define REG_INFRA_MISC 0xf00