linux/rtc/ds1685.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
4  * DS1685/DS1687-series RTC chips.
8  * include larger, battery-backed NV-SRAM, burst-mode access, and an RTC
11  * Copyright (C) 2011-2014 Joshua Kinard <kumba@gentoo.org>.
12  * Copyright (C) 2009 Matthias Fuchs <matthias.fuchs@esd-electronics.com>.
15  *    DS1685/DS1687 3V/5V Real-Time Clocks, 19-5215, Rev 4/10.
16  *    DS17x85/DS17x87 3V/5V Real-Time Clocks, 19-5222, Rev 4/10.
17  *    DS1689/DS1693 3V/5V Serialized Real-Time Clocks, Rev 112105.
29  * struct ds1685_priv - DS1685 private data structure.
38  * @prepare_poweroff: pointer to platform pre-poweroff function.
40  * @post_ram_clear: pointer to platform post ram-clear function.
58  * struct ds1685_rtc_platform_data - platform data structure.
59  * @plat_prepare_poweroff: platform-specific pre-poweroff function.
60  * @plat_wake_alarm: platform-specific wake alarm function.
61  * @plat_post_ram_clear: platform-specific post ram-clear function.
86 #define RTC_SECS		0x00	/* Seconds 00-59 */
87 #define RTC_SECS_ALARM		0x01	/* Alarm Seconds 00-59 */
88 #define RTC_MINS		0x02	/* Minutes 00-59 */
89 #define RTC_MINS_ALARM		0x03	/* Alarm Minutes 00-59 */
90 #define RTC_HRS			0x04	/* Hours 01-12 AM/PM || 00-23 */
91 #define RTC_HRS_ALARM		0x05	/* Alarm Hours 01-12 AM/PM || 00-23 */
92 #define RTC_WDAY		0x06	/* Day of Week 01-07 */
93 #define RTC_MDAY		0x07	/* Day of Month 01-31 */
94 #define RTC_MONTH		0x08	/* Month 01-12 */
95 #define RTC_YEAR		0x09	/* Year 00-99 */
96 #define RTC_CENTURY		0x48	/* Century 00-99 */
97 #define RTC_MDAY_ALARM		0x49	/* Alarm Day of Month 01-31 */
103 #define RTC_SECS_BCD_MASK	0x7f	/* - x x x x x x x */
104 #define RTC_MINS_BCD_MASK	0x7f	/* - x x x x x x x */
105 #define RTC_HRS_12_BCD_MASK	0x1f	/* - - - x x x x x */
106 #define RTC_HRS_24_BCD_MASK	0x3f	/* - - x x x x x x */
107 #define RTC_MDAY_BCD_MASK	0x3f	/* - - x x x x x x */
108 #define RTC_MONTH_BCD_MASK	0x1f	/* - - - x x x x x */
114 #define RTC_SECS_BIN_MASK	0x3f	/* - - x x x x x x */
115 #define RTC_MINS_BIN_MASK	0x3f	/* - - x x x x x x */
116 #define RTC_HRS_12_BIN_MASK	0x0f	/* - - - - x x x x */
117 #define RTC_HRS_24_BIN_MASK	0x1f	/* - - - x x x x x */
118 #define RTC_MDAY_BIN_MASK	0x1f	/* - - - x x x x x */
119 #define RTC_MONTH_BIN_MASK	0x0f	/* - - - - x x x x */
120 #define RTC_YEAR_BIN_MASK	0x7f	/* - x x x x x x x */
125 #define RTC_WDAY_MASK		0x07	/* - - - - - x x x */
150 #define RTC_CTRL_A_RS2		BIT(2)	/* Rate-Selection Bit 2 */
151 #define RTC_CTRL_A_RS3		BIT(3)	/* Rate-Selection Bit 3 */
152 #define RTC_CTRL_A_RS1		BIT(1)	/* Rate-Selection Bit 1 */
153 #define RTC_CTRL_A_RS0		BIT(0)	/* Rate-Selection Bit 0 */
160 #define RTC_CTRL_B_PIE		BIT(6)	/* Periodic-Interrupt Enable */
161 #define RTC_CTRL_B_AIE		BIT(5)	/* Alarm-Interrupt Enable */
162 #define RTC_CTRL_B_UIE		BIT(4)	/* Update-Ended Interrupt-Enable */
163 #define RTC_CTRL_B_SQWE		BIT(3)	/* Square-Wave Enable */
165 #define RTC_CTRL_B_2412		BIT(1)	/* 12-Hr/24-Hr Mode */
176 #define RTC_CTRL_C_IRQF		BIT(7)	/* Interrupt-Request Flag */
177 #define RTC_CTRL_C_PF		BIT(6)	/* Periodic-Interrupt Flag */
178 #define RTC_CTRL_C_AF		BIT(5)	/* Alarm-Interrupt Flag */
179 #define RTC_CTRL_C_UF		BIT(4)	/* Update-Ended Interrupt Flag */
199  * On the DS17x85/DS17x87, BIT(5) is Burst-Mode Enable (BME), and allows
200  * access to the extended NV-SRAM by automatically incrementing the address
203 #define RTC_CTRL_4A_VRT2	BIT(7)	/* Auxillary Battery Status */
204 #define RTC_CTRL_4A_INCR	BIT(6)	/* Increment-in-Progress Status */
205 #define RTC_CTRL_4A_PAB		BIT(3)	/* Power-Active Bar Control */
206 #define RTC_CTRL_4A_RF		BIT(2)	/* RAM-Clear Flag */
207 #define RTC_CTRL_4A_WF		BIT(1)	/* Wake-Up Alarm Flag */
210 #define RTC_CTRL_4A_BME		BIT(5)	/* Burst-Mode Enable */
218 #define RTC_CTRL_4B_ABE		BIT(7)	/* Auxillary Battery Enable */
221 #define RTC_CTRL_4B_RCE		BIT(4)	/* RAM Clear-Enable */
222 #define RTC_CTRL_4B_PRS		BIT(3)	/* PAB Reset-Select */
223 #define RTC_CTRL_4B_RIE		BIT(2)	/* RAM Clear-Interrupt Enable */
224 #define RTC_CTRL_4B_WIE		BIT(1)	/* Wake-Up Alarm-Interrupt Enable */
225 #define RTC_CTRL_4B_KSE		BIT(0)	/* Kickstart Interrupt-Enable */
247  * Model-specific registers in Bank 1.
253  * DS1685/DS1687   - Extended NV-SRAM address (LSB only).
254  * DS1689/DS1693   - Vcc, Vbat, Pwr Cycle Counters & Customer-specific S/N.
255  * DS17x85/DS17x87 - Extended NV-SRAM addresses (MSB & LSB) & Write counter.
258 #define RTC_BANK1_RAM_ADDR	0x50	/* NV-SRAM Addr */
266 #define RTC_BANK1_UNIQ_SN	0x60	/* Customer-specific S/N */
268 #define RTC_BANK1_RAM_ADDR_LSB	0x50	/* NV-SRAM Addr (LSB) */
269 #define RTC_BANK1_RAM_ADDR_MSB	0x51	/* NV-SRAM Addr (MSB) */
289  * Periodic Interrupt Rates / Square-Wave Output Frequency
291  * Periodic rates are selected by setting the RS3-RS0 bits in Control
295  * E32K overrides the settings of RS3-RS0 and outputs a frequency of 32768Hz
297  * the 1-of-16 decoder is only able to divide the base 32768Hz signal into 13
302  * /dev/rtc will return -EINVAL.  This also applies if the periodic interrupt
305  * Not currently used by the rtc-ds1685 driver because the RTC core removed
306  * support for hardware-generated periodic-interrupts in favour of
307  * hrtimer-generated interrupts.  But these defines are kept around for use
309  * hardware-generated periodic interrupts are ever added back.
326 #define RTC_SQW_32768HZ		32768	/*  1    -   -   -   -  */
332  *   - 50 bytes of NVRAM are available just past the clock registers.
333  *   - 64 additional bytes are available in Bank0.
335  * Extended, battery-backed NV-SRAM:
336  *   - DS1685/DS1687    - 128 bytes.
337  *   - DS1689/DS1693    - 0 bytes.
338  *   - DS17285/DS17287  - 2048 bytes.
339  *   - DS17485/DS17487  - 4096 bytes.
340  *   - DS17885/DS17887  - 8192 bytes.