Lines Matching +full:0 +full:x7f
10 PCA9450_TYPE_PCA9450A = 0,
17 PCA9450_BUCK1 = 0,
32 PCA9450_DVS_LEVEL_RUN = 0,
37 #define PCA9450_BUCK1_VOLTAGE_NUM 0x80
38 #define PCA9450_BUCK2_VOLTAGE_NUM 0x80
39 #define PCA9450_BUCK3_VOLTAGE_NUM 0x80
40 #define PCA9450_BUCK4_VOLTAGE_NUM 0x80
42 #define PCA9450_BUCK5_VOLTAGE_NUM 0x80
43 #define PCA9450_BUCK6_VOLTAGE_NUM 0x80
45 #define PCA9450_LDO1_VOLTAGE_NUM 0x08
46 #define PCA9450_LDO2_VOLTAGE_NUM 0x08
47 #define PCA9450_LDO3_VOLTAGE_NUM 0x20
48 #define PCA9450_LDO4_VOLTAGE_NUM 0x20
49 #define PCA9450_LDO5_VOLTAGE_NUM 0x10
52 PCA9450_REG_DEV_ID = 0x00,
53 PCA9450_REG_INT1 = 0x01,
54 PCA9450_REG_INT1_MSK = 0x02,
55 PCA9450_REG_STATUS1 = 0x03,
56 PCA9450_REG_STATUS2 = 0x04,
57 PCA9450_REG_PWRON_STAT = 0x05,
58 PCA9450_REG_SWRST = 0x06,
59 PCA9450_REG_PWRCTRL = 0x07,
60 PCA9450_REG_RESET_CTRL = 0x08,
61 PCA9450_REG_CONFIG1 = 0x09,
62 PCA9450_REG_CONFIG2 = 0x0A,
63 PCA9450_REG_BUCK123_DVS = 0x0C,
64 PCA9450_REG_BUCK1OUT_LIMIT = 0x0D,
65 PCA9450_REG_BUCK2OUT_LIMIT = 0x0E,
66 PCA9450_REG_BUCK3OUT_LIMIT = 0x0F,
67 PCA9450_REG_BUCK1CTRL = 0x10,
68 PCA9450_REG_BUCK1OUT_DVS0 = 0x11,
69 PCA9450_REG_BUCK1OUT_DVS1 = 0x12,
70 PCA9450_REG_BUCK2CTRL = 0x13,
71 PCA9450_REG_BUCK2OUT_DVS0 = 0x14,
72 PCA9450_REG_BUCK2OUT_DVS1 = 0x15,
73 PCA9450_REG_BUCK3CTRL = 0x16,
74 PCA9450_REG_BUCK3OUT_DVS0 = 0x17,
75 PCA9450_REG_BUCK3OUT_DVS1 = 0x18,
76 PCA9450_REG_BUCK4CTRL = 0x19,
77 PCA9450_REG_BUCK4OUT = 0x1A,
78 PCA9450_REG_BUCK5CTRL = 0x1B,
79 PCA9450_REG_BUCK5OUT = 0x1C,
80 PCA9450_REG_BUCK6CTRL = 0x1D,
81 PCA9450_REG_BUCK6OUT = 0x1E,
82 PCA9450_REG_LDO_AD_CTRL = 0x20,
83 PCA9450_REG_LDO1CTRL = 0x21,
84 PCA9450_REG_LDO2CTRL = 0x22,
85 PCA9450_REG_LDO3CTRL = 0x23,
86 PCA9450_REG_LDO4CTRL = 0x24,
87 PCA9450_REG_LDO5CTRL_L = 0x25,
88 PCA9450_REG_LDO5CTRL_H = 0x26,
89 PCA9450_REG_LOADSW_CTRL = 0x2A,
90 PCA9450_REG_VRFLT1_STS = 0x2B,
91 PCA9450_REG_VRFLT2_STS = 0x2C,
92 PCA9450_REG_VRFLT1_MASK = 0x2D,
93 PCA9450_REG_VRFLT2_MASK = 0x2E,
94 PCA9450_MAX_REGISTER = 0x2F,
98 #define BUCK_ENMODE_OFF 0x00
99 #define BUCK_ENMODE_ONREQ 0x01
100 #define BUCK_ENMODE_ONREQ_STBYREQ 0x02
101 #define BUCK_ENMODE_ON 0x03
104 #define BUCK1_RAMP_MASK 0xC0
105 #define BUCK1_RAMP_25MV 0x0
106 #define BUCK1_RAMP_12P5MV 0x1
107 #define BUCK1_RAMP_6P25MV 0x2
108 #define BUCK1_RAMP_3P125MV 0x3
109 #define BUCK1_DVS_CTRL 0x10
110 #define BUCK1_AD 0x08
111 #define BUCK1_FPWM 0x04
112 #define BUCK1_ENMODE_MASK 0x03
115 #define BUCK2_RAMP_MASK 0xC0
116 #define BUCK2_RAMP_25MV 0x0
117 #define BUCK2_RAMP_12P5MV 0x1
118 #define BUCK2_RAMP_6P25MV 0x2
119 #define BUCK2_RAMP_3P125MV 0x3
120 #define BUCK2_DVS_CTRL 0x10
121 #define BUCK2_AD 0x08
122 #define BUCK2_FPWM 0x04
123 #define BUCK2_ENMODE_MASK 0x03
126 #define BUCK3_RAMP_MASK 0xC0
127 #define BUCK3_RAMP_25MV 0x0
128 #define BUCK3_RAMP_12P5MV 0x1
129 #define BUCK3_RAMP_6P25MV 0x2
130 #define BUCK3_RAMP_3P125MV 0x3
131 #define BUCK3_DVS_CTRL 0x10
132 #define BUCK3_AD 0x08
133 #define BUCK3_FPWM 0x04
134 #define BUCK3_ENMODE_MASK 0x03
137 #define BUCK4_AD 0x08
138 #define BUCK4_FPWM 0x04
139 #define BUCK4_ENMODE_MASK 0x03
142 #define BUCK5_AD 0x08
143 #define BUCK5_FPWM 0x04
144 #define BUCK5_ENMODE_MASK 0x03
147 #define BUCK6_AD 0x08
148 #define BUCK6_FPWM 0x04
149 #define BUCK6_ENMODE_MASK 0x03
152 #define BUCK123_PRESET_EN 0x80
155 #define BUCK1OUT_DVS0_MASK 0x7F
156 #define BUCK1OUT_DVS0_DEFAULT 0x14
159 #define BUCK1OUT_DVS1_MASK 0x7F
160 #define BUCK1OUT_DVS1_DEFAULT 0x14
163 #define BUCK2OUT_DVS0_MASK 0x7F
164 #define BUCK2OUT_DVS0_DEFAULT 0x14
167 #define BUCK2OUT_DVS1_MASK 0x7F
168 #define BUCK2OUT_DVS1_DEFAULT 0x14
171 #define BUCK3OUT_DVS0_MASK 0x7F
172 #define BUCK3OUT_DVS0_DEFAULT 0x14
175 #define BUCK3OUT_DVS1_MASK 0x7F
176 #define BUCK3OUT_DVS1_DEFAULT 0x14
179 #define BUCK4OUT_MASK 0x7F
180 #define BUCK4OUT_DEFAULT 0x6C
183 #define BUCK5OUT_MASK 0x7F
184 #define BUCK5OUT_DEFAULT 0x30
187 #define BUCK6OUT_MASK 0x7F
188 #define BUCK6OUT_DEFAULT 0x14
191 #define LDO1_EN_MASK 0xC0
192 #define LDO1OUT_MASK 0x07
195 #define LDO2_EN_MASK 0xC0
196 #define LDO2OUT_MASK 0x07
199 #define LDO3_EN_MASK 0xC0
200 #define LDO3OUT_MASK 0x1F
203 #define LDO4_EN_MASK 0xC0
204 #define LDO4OUT_MASK 0x1F
207 #define LDO5L_EN_MASK 0xC0
208 #define LDO5LOUT_MASK 0x0F
210 #define LDO5H_EN_MASK 0xC0
211 #define LDO5HOUT_MASK 0x0F
214 #define IRQ_PWRON 0x80
215 #define IRQ_WDOGB 0x40
216 #define IRQ_RSVD 0x20
217 #define IRQ_VR_FLT1 0x10
218 #define IRQ_VR_FLT2 0x08
219 #define IRQ_LOWVSYS 0x04
220 #define IRQ_THERM_105 0x02
221 #define IRQ_THERM_125 0x01
224 #define WDOG_B_CFG_MASK 0xC0
225 #define WDOG_B_CFG_NONE 0x00
226 #define WDOG_B_CFG_WARM 0x40
227 #define WDOG_B_CFG_COLD_LDO12 0x80
228 #define WDOG_B_CFG_COLD 0xC0
231 #define I2C_LT_MASK 0x03
232 #define I2C_LT_FORCE_DISABLE 0x00
233 #define I2C_LT_ON_STANDBY_RUN 0x01
234 #define I2C_LT_ON_RUN 0x02
235 #define I2C_LT_FORCE_ENABLE 0x03