Lines Matching +full:0 +full:x1f00000
16 #define PTR_LO(x) ((u32)(((uintptr_t)(x)) & 0xffffffff))
23 } while (0)
47 #define ISCSI_CDU_TASK_SEG_TYPE 0
48 #define FCOE_CDU_TASK_SEG_TYPE 0
59 #define YSTORM_QZONE_SIZE 0
60 #define PSTORM_QZONE_SIZE 0
97 #define FW_ENGINEERING_VERSION 0
158 #define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
161 #define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
163 #define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0)
169 #define CDU_CONTEXT_VALIDATION_DEFAULT_CFG (0x3d)
176 #define DQ_DEMS_LEGACY 0
182 #define DQ_XCM_AGG_VAL_SEL_WORD2 0
213 #define DQ_UCM_AGG_VAL_SEL_WORD0 0
229 #define DQ_TCM_AGG_VAL_SEL_WORD0 0
245 #define DQ_XCM_AGG_FLG_SHIFT_BIT14 0
270 #define DQ_UCM_AGG_FLG_SHIFT_CF0 0
289 #define DQ_TCM_AGG_FLG_SHIFT_CF0 0
308 #define DQ_PWM_OFFSET_DPM_BASE 0x0
309 #define DQ_PWM_OFFSET_DPM_END 0x27
310 #define DQ_PWM_OFFSET_XCM32_24ICID_BASE 0x28
311 #define DQ_PWM_OFFSET_UCM32_24ICID_BASE 0x30
312 #define DQ_PWM_OFFSET_TCM32_24ICID_BASE 0x38
313 #define DQ_PWM_OFFSET_XCM16_BASE 0x40
314 #define DQ_PWM_OFFSET_XCM32_BASE 0x44
315 #define DQ_PWM_OFFSET_UCM16_BASE 0x48
316 #define DQ_PWM_OFFSET_UCM32_BASE 0x4C
317 #define DQ_PWM_OFFSET_UCM16_4 0x50
318 #define DQ_PWM_OFFSET_TCM16_BASE 0x58
319 #define DQ_PWM_OFFSET_TCM32_BASE 0x5C
320 #define DQ_PWM_OFFSET_XCM_FLAGS 0x68
321 #define DQ_PWM_OFFSET_UCM_FLAGS 0x69
322 #define DQ_PWM_OFFSET_TCM_FLAGS 0x6B
374 #define CM_TX_PQ_BASE 0x200
394 #define CAU_FSM_ETH_RX 0
403 #define CAU_HC_ENABLE_STATE 0
419 #define IGU_MEM_BASE 0x0000
421 #define IGU_MEM_MSIX_BASE 0x0000
422 #define IGU_MEM_MSIX_UPPER 0x0101
423 #define IGU_MEM_MSIX_RESERVED_UPPER 0x01ff
425 #define IGU_MEM_PBA_MSIX_BASE 0x0200
426 #define IGU_MEM_PBA_MSIX_UPPER 0x0202
427 #define IGU_MEM_PBA_MSIX_RESERVED_UPPER 0x03ff
429 #define IGU_CMD_INT_ACK_BASE 0x0400
430 #define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff
432 #define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0
433 #define IGU_CMD_ATTN_BIT_SET_UPPER 0x05f1
434 #define IGU_CMD_ATTN_BIT_CLR_UPPER 0x05f2
436 #define IGU_REG_SISR_MDPC_WMASK_UPPER 0x05f3
437 #define IGU_REG_SISR_MDPC_WMASK_LSB_UPPER 0x05f4
438 #define IGU_REG_SISR_MDPC_WMASK_MSB_UPPER 0x05f5
439 #define IGU_REG_SISR_MDPC_WOMASK_UPPER 0x05f6
441 #define IGU_CMD_PROD_UPD_BASE 0x0600
442 #define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff
449 #define PXP_BAR_GRC 0
450 #define PXP_BAR_TSDM 0
451 #define PXP_BAR_USDM 0
452 #define PXP_BAR_XSDM 0
453 #define PXP_BAR_MSDM 0
454 #define PXP_BAR_YSDM 0
455 #define PXP_BAR_PSDM 0
456 #define PXP_BAR_IGU 0
464 #define PXP_PF_WINDOW_ADMIN_START 0
465 #define PXP_PF_WINDOW_ADMIN_LENGTH 0x1000
468 #define PXP_PF_WINDOW_ADMIN_PER_PF_START 0
473 #define PXP_PF_WINDOW_ADMIN_GLOBAL_START 0x200
479 #define PXP_PF_GLOBAL_PRETEND_ADDR 0x1f0
480 #define PXP_PF_ME_OPAQUE_MASK_ADDR 0xf4
481 #define PXP_PF_ME_OPAQUE_ADDR 0x1f8
482 #define PXP_PF_ME_CONCRETE_ADDR 0x1fc
485 #define PXP_EXTERNAL_BAR_PF_WINDOW_START 0x1000
487 #define PXP_EXTERNAL_BAR_PF_WINDOW_SINGLE_SIZE 0x1000
498 #define PXP_EXTERNAL_BAR_GLOBAL_WINDOW_SINGLE_SIZE 0x1000
507 #define PXP_BAR0_START_GRC 0x0000
508 #define PXP_BAR0_GRC_LENGTH 0x1C00000
512 #define PXP_BAR0_START_IGU 0x1C00000
513 #define PXP_BAR0_IGU_LENGTH 0x10000
517 #define PXP_BAR0_START_TSDM 0x1C80000
518 #define PXP_BAR0_SDM_LENGTH 0x40000
519 #define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000
523 #define PXP_BAR0_START_MSDM 0x1D00000
527 #define PXP_BAR0_START_USDM 0x1D80000
531 #define PXP_BAR0_START_XSDM 0x1E00000
535 #define PXP_BAR0_START_YSDM 0x1E80000
539 #define PXP_BAR0_START_PSDM 0x1F00000
546 #define PXP_VF_BAR0 0
548 #define PXP_VF_BAR0_START_IGU 0
549 #define PXP_VF_BAR0_IGU_LENGTH 0x3000
553 #define PXP_VF_BAR0_START_DQ 0x3000
554 #define PXP_VF_BAR0_DQ_LENGTH 0x200
555 #define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0
563 #define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200
564 #define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200
568 #define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400
572 #define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600
576 #define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800
580 #define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00
584 #define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00
588 #define PXP_VF_BAR0_START_GRC 0x3E00
589 #define PXP_VF_BAR0_GRC_LENGTH 0x200
593 #define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000
594 #define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000
596 #define PXP_VF_BAR0_START_IGU2 0x10000
597 #define PXP_VF_BAR0_IGU2_LENGTH 0xD000
623 #define SDM_OP_GEN_TRIG_NONE 0
634 #define SDM_COMP_TYPE_NONE 0
664 #define COALESCING_TIMESET_TIMESET_MASK 0x7F
665 #define COALESCING_TIMESET_TIMESET_SHIFT 0
666 #define COALESCING_TIMESET_VALID_MASK 0x1
685 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_MASK 0x1
686 #define TCP_ULP_CONNECT_DONE_PARAMS_TS_EN_SHIFT 0
687 #define TCP_ULP_CONNECT_DONE_PARAMS_RESERVED_MASK 0x7F
703 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_MASK 0x3F
704 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_SHIFT 0
705 #define ISCSI_EQE_DATA_ERROR_PDU_OPCODE_VALID_MASK 0x1
707 #define ISCSI_EQE_DATA_RESERVED0_MASK 0x1
798 #define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF
799 #define CAU_PI_ENTRY_PROD_VAL_SHIFT 0
800 #define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F
802 #define CAU_PI_ENTRY_FSM_SEL_MASK 0x1
804 #define CAU_PI_ENTRY_RESERVED_MASK 0xFF
811 #define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF
812 #define CAU_SB_ENTRY_SB_PROD_SHIFT 0
813 #define CAU_SB_ENTRY_STATE0_MASK 0xF
815 #define CAU_SB_ENTRY_STATE1_MASK 0xF
818 #define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F
819 #define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0
820 #define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F
822 #define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3
824 #define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3
826 #define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF
828 #define CAU_SB_ENTRY_VF_VALID_MASK 0x1
830 #define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF
832 #define CAU_SB_ENTRY_TPH_MASK 0x1
840 IGU_COMMAND_TYPE_NOP = 0,
848 #define CORE_DB_DATA_DEST_MASK 0x3
849 #define CORE_DB_DATA_DEST_SHIFT 0
850 #define CORE_DB_DATA_AGG_CMD_MASK 0x3
852 #define CORE_DB_DATA_BYPASS_EN_MASK 0x1
854 #define CORE_DB_DATA_RESERVED_MASK 0x1
856 #define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3
894 #define DB_L2_DPM_DATA_SIZE_MASK 0x3F
895 #define DB_L2_DPM_DATA_SIZE_SHIFT 0
896 #define DB_L2_DPM_DATA_DPM_TYPE_MASK 0x3
898 #define DB_L2_DPM_DATA_NUM_BDS_MASK 0xFF
900 #define DB_L2_DPM_DATA_PKT_SIZE_MASK 0x7FF
902 #define DB_L2_DPM_DATA_RESERVED0_MASK 0x1
904 #define DB_L2_DPM_DATA_SGE_NUM_MASK 0x7
906 #define DB_L2_DPM_DATA_TGFS_SRC_EN_MASK 0x1
915 #define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF
916 #define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0
917 #define DB_L2_DPM_SGE_RESERVED0_MASK 0x3
919 #define DB_L2_DPM_SGE_ST_VALID_MASK 0x1
921 #define DB_L2_DPM_SGE_RESERVED1_MASK 0xF
929 #define DB_LEGACY_ADDR_RESERVED0_MASK 0x3
930 #define DB_LEGACY_ADDR_RESERVED0_SHIFT 0
931 #define DB_LEGACY_ADDR_DEMS_MASK 0x7
933 #define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF
940 #define DB_LEGACY_WO_DEMS_ADDR_RESERVED0_MASK 0x3
941 #define DB_LEGACY_WO_DEMS_ADDR_RESERVED0_SHIFT 0
942 #define DB_LEGACY_WO_DEMS_ADDR_ICID_MASK 0x3FFFFFFF
949 #define DB_PWM_ADDR_RESERVED0_MASK 0x7
950 #define DB_PWM_ADDR_RESERVED0_SHIFT 0
951 #define DB_PWM_ADDR_OFFSET_MASK 0x7F
953 #define DB_PWM_ADDR_WID_MASK 0x3
955 #define DB_PWM_ADDR_DPI_MASK 0xFFFF
957 #define DB_PWM_ADDR_RESERVED1_MASK 0xF
964 #define DB_RDMA_24B_ICID_DPM_PARAMS_SIZE_MASK 0x3F
965 #define DB_RDMA_24B_ICID_DPM_PARAMS_SIZE_SHIFT 0
966 #define DB_RDMA_24B_ICID_DPM_PARAMS_DPM_TYPE_MASK 0x3
968 #define DB_RDMA_24B_ICID_DPM_PARAMS_OPCODE_MASK 0xFF
970 #define DB_RDMA_24B_ICID_DPM_PARAMS_ICID_EXT_MASK 0xFF
972 #define DB_RDMA_24B_ICID_DPM_PARAMS_INV_BYTE_CNT_MASK 0x7
974 #define DB_RDMA_24B_ICID_DPM_PARAMS_EXT_ICID_MODE_EN_MASK 0x1
976 #define DB_RDMA_24B_ICID_DPM_PARAMS_COMPLETION_FLG_MASK 0x1
978 #define DB_RDMA_24B_ICID_DPM_PARAMS_S_FLG_MASK 0x1
980 #define DB_RDMA_24B_ICID_DPM_PARAMS_RESERVED1_MASK 0x1
982 #define DB_RDMA_24B_ICID_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1
989 #define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F
990 #define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0
991 #define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3
993 #define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF
995 #define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF
997 #define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1
999 #define DB_RDMA_DPM_PARAMS_ACK_REQUEST_MASK 0x1
1001 #define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1
1003 #define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1
1005 #define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1
1020 IGU_INT_ENABLE = 0,
1030 #define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF
1031 #define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0
1032 #define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1
1034 #define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3
1036 #define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1
1038 #define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1
1040 #define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3
1042 #define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1
1049 IGU_SEG_ACCESS_REG = 0,
1055 * L3Type: 0 - unknown (not ip), 1 - Ipv4, 2 - Ipv6
1066 * L4-protocol: 0 - none, 1 - TCP, 2 - UDP.
1080 #define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3
1081 #define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0
1082 #define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3
1084 #define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1
1086 #define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1
1088 #define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1
1090 #define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1
1092 #define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1
1094 #define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1
1096 #define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1
1098 #define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1
1100 #define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1
1102 #define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1
1104 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1
1106 #define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1
1113 #define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1
1114 #define PARSING_ERR_FLAGS_MAC_ERROR_SHIFT 0
1115 #define PARSING_ERR_FLAGS_TRUNC_ERROR_MASK 0x1
1117 #define PARSING_ERR_FLAGS_PKT_TOO_SMALL_MASK 0x1
1119 #define PARSING_ERR_FLAGS_ANY_HDR_MISSING_TAG_MASK 0x1
1121 #define PARSING_ERR_FLAGS_ANY_HDR_IP_VER_MISMTCH_MASK 0x1
1123 #define PARSING_ERR_FLAGS_ANY_HDR_IP_V4_HDR_LEN_TOO_SMALL_MASK 0x1
1125 #define PARSING_ERR_FLAGS_ANY_HDR_IP_BAD_TOTAL_LEN_MASK 0x1
1127 #define PARSING_ERR_FLAGS_IP_V4_CHKSM_ERROR_MASK 0x1
1129 #define PARSING_ERR_FLAGS_ANY_HDR_L4_IP_LEN_MISMTCH_MASK 0x1
1131 #define PARSING_ERR_FLAGS_ZERO_UDP_IP_V6_CHKSM_MASK 0x1
1133 #define PARSING_ERR_FLAGS_INNER_L4_CHKSM_ERROR_MASK 0x1
1135 #define PARSING_ERR_FLAGS_ANY_HDR_ZERO_TTL_OR_HOP_LIM_MASK 0x1
1137 #define PARSING_ERR_FLAGS_NON_8021Q_TAG_EXISTS_IN_BOTH_HDRS_MASK 0x1
1139 #define PARSING_ERR_FLAGS_GENEVE_OPTION_OVERSIZED_MASK 0x1
1141 #define PARSING_ERR_FLAGS_TUNNEL_IP_V4_CHKSM_ERROR_MASK 0x1
1143 #define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_MASK 0x1
1155 #define PXP_CONCRETE_FID_PFID_MASK 0xF
1156 #define PXP_CONCRETE_FID_PFID_SHIFT 0
1157 #define PXP_CONCRETE_FID_PORT_MASK 0x3
1159 #define PXP_CONCRETE_FID_PATH_MASK 0x1
1161 #define PXP_CONCRETE_FID_VFVALID_MASK 0x1
1163 #define PXP_CONCRETE_FID_VFID_MASK 0xFF
1170 #define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF
1171 #define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0
1172 #define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7
1174 #define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1
1176 #define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF
1190 #define PXP_PRETEND_CMD_PATH_MASK 0x1
1191 #define PXP_PRETEND_CMD_PATH_SHIFT 0
1192 #define PXP_PRETEND_CMD_USE_PORT_MASK 0x1
1194 #define PXP_PRETEND_CMD_PORT_MASK 0x3
1196 #define PXP_PRETEND_CMD_RESERVED0_MASK 0xF
1198 #define PXP_PRETEND_CMD_RESERVED1_MASK 0xF
1200 #define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1
1202 #define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1
1204 #define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1
1206 #define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1
1213 #define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF
1214 #define PXP_PTT_ENTRY_OFFSET_SHIFT 0
1215 #define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF
1223 #define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF
1224 #define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0
1225 #define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1
1227 #define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F
1229 #define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF
1239 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1
1240 #define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0
1241 #define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1
1243 #define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1
1245 #define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1
1247 #define RDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3
1249 #define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
1251 #define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1
1258 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1
1259 #define RDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0
1260 #define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1
1262 #define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1
1264 #define RDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1
1266 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1
1268 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1
1270 #define RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7
1272 #define RDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3
1274 #define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1
1276 #define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1
1278 #define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1
1280 #define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1
1282 #define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1
1285 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_MASK 0xF
1286 #define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_SHIFT 0
1287 #define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_MASK 0xF
1289 #define RDIF_TASK_CONTEXT_ERROR_IN_IO_MASK 0x1
1291 #define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_MASK 0x1
1293 #define RDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF
1295 #define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3
1303 #define SRC_ENTRY_HEADER_NEXT_PTR_TYPE_MASK 0x1
1304 #define SRC_ENTRY_HEADER_NEXT_PTR_TYPE_SHIFT 0
1305 #define SRC_ENTRY_HEADER_EMPTY_MASK 0x1
1307 #define SRC_ENTRY_HEADER_RESERVED_MASK 0x3FFFFFFF
1324 #define STATUS_BLOCK_SB_NUM_MASK 0x1FF
1325 #define STATUS_BLOCK_SB_NUM_SHIFT 0
1326 #define STATUS_BLOCK_ZERO_PAD_MASK 0x7F
1328 #define STATUS_BLOCK_ZERO_PAD2_MASK 0xFFFF
1331 #define STATUS_BLOCK_PROD_INDEX_MASK 0xFFFFFF
1332 #define STATUS_BLOCK_PROD_INDEX_SHIFT 0
1333 #define STATUS_BLOCK_ZERO_PAD3_MASK 0xFF
1345 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_MASK 0xF
1346 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_SHIFT 0
1347 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_MASK 0xF
1349 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_MASK 0x1
1351 #define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_MASK 0x1
1353 #define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F
1357 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1
1358 #define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0
1359 #define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1
1361 #define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1
1363 #define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1
1365 #define TDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3
1367 #define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
1369 #define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1
1372 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1
1373 #define TDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0
1374 #define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1
1376 #define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1
1378 #define TDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1
1380 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1
1382 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1
1384 #define TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7
1386 #define TDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3
1388 #define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1
1390 #define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1
1392 #define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1
1394 #define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_MASK 0xF
1396 #define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_MASK 0xF
1398 #define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_MASK 0x1
1400 #define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_MASK 0x1
1402 #define TDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF
1404 #define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1
1406 #define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1
1408 #define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1
1410 #define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1
1423 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF
1424 #define TIMERS_CONTEXT_EXPIRATIONTIMELC0_SHIFT 0
1425 #define TIMERS_CONTEXT_RESERVED0_MASK 0x1
1427 #define TIMERS_CONTEXT_VALIDLC0_MASK 0x1
1429 #define TIMERS_CONTEXT_ACTIVELC0_MASK 0x1
1431 #define TIMERS_CONTEXT_RESERVED1_MASK 0x3
1434 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_MASK 0x7FFFFFF
1435 #define TIMERS_CONTEXT_EXPIRATIONTIMELC1_SHIFT 0
1436 #define TIMERS_CONTEXT_RESERVED2_MASK 0x1
1438 #define TIMERS_CONTEXT_VALIDLC1_MASK 0x1
1440 #define TIMERS_CONTEXT_ACTIVELC1_MASK 0x1
1442 #define TIMERS_CONTEXT_RESERVED3_MASK 0x3
1445 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_MASK 0x7FFFFFF
1446 #define TIMERS_CONTEXT_EXPIRATIONTIMELC2_SHIFT 0
1447 #define TIMERS_CONTEXT_RESERVED4_MASK 0x1
1449 #define TIMERS_CONTEXT_VALIDLC2_MASK 0x1
1451 #define TIMERS_CONTEXT_ACTIVELC2_MASK 0x1
1453 #define TIMERS_CONTEXT_RESERVED5_MASK 0x3
1456 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_MASK 0x7FFFFFF
1457 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALUE_SHIFT 0
1458 #define TIMERS_CONTEXT_RESERVED6_MASK 0x1
1460 #define TIMERS_CONTEXT_HOSTEXPRIRATIONVALID_MASK 0x1
1462 #define TIMERS_CONTEXT_RESERVED7_MASK 0x7
1468 e_unknown = 0,