Lines Matching +full:0 +full:xfffffe00

13 #define	PCI_DEVICE_ID_VLV_PMC	0x0F1C
15 #define	PCI_DEVICE_ID_CHT_PMC	0x229C
18 #define	PMC_BASE_ADDR_OFFSET	0x44
19 #define	PMC_BASE_ADDR_MASK	0xFFFFFE00
20 #define	PMC_MMIO_REG_LEN	0x100
24 #define	PMC_FUNC_DIS		0x34
25 #define	PMC_FUNC_DIS_2		0x38
32 #define	PMC_S0IX_WAKE_EN	0x3C
47 #define PMC_CLK_CTL_OFFSET		0x60
50 #define PMC_CLK_CTL_GATED_ON_D3		0x0
51 #define PMC_CLK_CTL_FORCE_ON		0x1
52 #define PMC_CLK_CTL_FORCE_OFF		0x2
53 #define PMC_CLK_CTL_RESERVED		0x3
54 #define PMC_MASK_CLK_CTL		GENMASK(1, 0)
56 #define PMC_CLK_FREQ_XTAL		(0 << 2)	/* 25 MHz */
60 #define	PMC_S0IR_TMR		0x80
61 #define	PMC_S0I1_TMR		0x84
62 #define	PMC_S0I2_TMR		0x88
63 #define	PMC_S0I3_TMR		0x8C
64 #define	PMC_S0_TMR		0x90
69 #define	PMC_PSS			0x98
71 #define PMC_PSS_BIT_GBE			BIT(0)
106 #define	PMC_D3_STS_0		0xA0
108 #define	BIT_LPSS1_F0_DMA	BIT(0)
141 #define	PMC_D3_STS_1		0xA4
142 #define	BIT_SMB			BIT(0)
152 #define	ACPI_BASE_ADDR_OFFSET	0x40
153 #define	ACPI_BASE_ADDR_MASK	0xFFFFFE00
154 #define	ACPI_MMIO_REG_LEN	0x100
156 #define	PM1_CNT			0x4
158 #define	SLEEP_TYPE_S5		0x1C00