31 	u8			sup_pclk;	/* 1 :SH7757, 0: SH7724/SH7372 */
36 #define MMCIF_CE_CMD_SET	0x00000000
37 #define MMCIF_CE_ARG		0x00000008
38 #define MMCIF_CE_ARG_CMD12	0x0000000C
39 #define MMCIF_CE_CMD_CTRL	0x00000010
40 #define MMCIF_CE_BLOCK_SET	0x00000014
41 #define MMCIF_CE_CLK_CTRL	0x00000018
42 #define MMCIF_CE_BUF_ACC	0x0000001C
43 #define MMCIF_CE_RESP3		0x00000020
44 #define MMCIF_CE_RESP2		0x00000024
45 #define MMCIF_CE_RESP1		0x00000028
46 #define MMCIF_CE_RESP0		0x0000002C
47 #define MMCIF_CE_RESP_CMD12	0x00000030
48 #define MMCIF_CE_DATA		0x00000034
49 #define MMCIF_CE_INT		0x00000040
50 #define MMCIF_CE_INT_MASK	0x00000044
51 #define MMCIF_CE_HOST_STS1	0x00000048
52 #define MMCIF_CE_HOST_STS2	0x0000004C
53 #define MMCIF_CE_CLK_CTRL2	0x00000070
54 #define MMCIF_CE_VERSION	0x0000007C
59 #define BUF_ACC_BUSW_32		(0 << 17)
65 #define CLK_CLEAR		(0xf << 16)
66 #define CLK_SUP_PCLK		(0xf << 16)
71 #define SRBSYTO_29		(0xf << 8) /* resp busy timeout */
72 #define SRWDTO_29		(0xf << 4) /* read/write timeout */
73 #define SCCSTO_29		(0xf << 0) /* ccs timeout */
77 #define SOFT_RST_OFF		0
94 	sh_mmcif_writel(base, MMCIF_CE_INT, 0);  in sh_mmcif_boot_cmd_send()
104 	for (cnt = 0; cnt < 1000000; cnt++) {  in sh_mmcif_boot_cmd_poll()
108 			return 0;  in sh_mmcif_boot_cmd_poll()
119 	return sh_mmcif_boot_cmd_poll(base, 0x00010000);  in sh_mmcif_boot_cmd()
129 	sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000);  in sh_mmcif_boot_do_read_single()
131 	if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900)  in sh_mmcif_boot_do_read_single()
135 	sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS);  in sh_mmcif_boot_do_read_single()
136 	if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0)  in sh_mmcif_boot_do_read_single()
139 	for (k = 0; k < (SH_MMCIF_BBS / 4); k++)  in sh_mmcif_boot_do_read_single()
142 	return 0;  in sh_mmcif_boot_do_read_single()
151 	int ret = 0;  in sh_mmcif_boot_do_read()
159 	sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);  in sh_mmcif_boot_do_read()
162 	sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);  in sh_mmcif_boot_do_read()
165 	sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);  in sh_mmcif_boot_do_read()
167 	for (k = 0; !ret && k < nr_blocks; k++)  in sh_mmcif_boot_do_read()
192 	sh_mmcif_boot_cmd(base, 0x00000040, 0);  in sh_mmcif_boot_init()
196 		sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */  in sh_mmcif_boot_init()
197 	} while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000)  in sh_mmcif_boot_init()
198 		 != 0x80000000);  in sh_mmcif_boot_init()
201 	sh_mmcif_boot_cmd(base, 0x02806040, 0);  in sh_mmcif_boot_init()
204 	sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);  in sh_mmcif_boot_init()