Lines Matching +full:clk +full:- +full:delay +full:- +full:cycles
1 /* SPDX-License-Identifier: GPL-2.0-only */
5 * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
28 * (which is in picoseconds), while the register values are in gpmc_fck cycles.
34 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
58 u32 page_burst_access; /* Multiple access word delay */
59 u32 access; /* Start-cycle to first data valid delay */
104 u32 clk; member
105 u32 t_bacc; /* burst access valid clock to output delay */
106 u32 t_ces; /* CS setup time to clk */
107 u32 t_avds; /* ADV setup time to clk */
108 u32 t_avdh; /* ADV hold time from clk */
109 u32 t_ach; /* address hold time from clk */
110 u32 t_rdyo; /* clk to ready valid */
113 u32 t_ce_avd; /* CS on to ADV on delay */
118 u8 cyc_aavdh_oe;/* read address hold time in cycles */
119 u8 cyc_aavdh_we;/* write address hold time in cycles */
120 u8 cyc_oe; /* access time from OE assertion in cycles */
121 u8 cyc_wpl; /* write deassertion time in cycles */
122 u32 cyc_iaa; /* initial access time in cycles */
134 #define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
135 #define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
136 #define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
137 #define GPMC_MUX_AD 2 /* Addr-Data multiplex */
158 u32 wait_pin; /* wait-pin to be used */