Lines Matching full:time

15 /* bool type time settings */
35 	u32 cs_on;		/* Assertion time */
36 	u32 cs_rd_off;		/* Read deassertion time */
37 	u32 cs_wr_off;		/* Write deassertion time */
40 	u32 adv_on;		/* Assertion time */
41 	u32 adv_rd_off;		/* Read deassertion time */
42 	u32 adv_wr_off;		/* Write deassertion time */
43 	u32 adv_aad_mux_on;	/* ADV assertion time for AAD */
44 	u32 adv_aad_mux_rd_off;	/* ADV read deassertion time for AAD */
45 	u32 adv_aad_mux_wr_off;	/* ADV write deassertion time for AAD */
48 	u32 we_on;		/* WE assertion time */
49 	u32 we_off;		/* WE deassertion time */
52 	u32 oe_on;		/* OE assertion time */
53 	u32 oe_off;		/* OE deassertion time */
54 	u32 oe_aad_mux_on;	/* OE assertion time for AAD */
55 	u32 oe_aad_mux_off;	/* OE deassertion time for AAD */
57 	/* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
60 	u32 rd_cycle;		/* Total read cycle time */
61 	u32 wr_cycle;		/* Total write cycle time */
87 	u32 t_avdp_r;	/* ADV low time (what about t_cer ?) */
89 	u32 t_aavdh;	/* address hold time */
91 	u32 t_aa;	/* access time from ADV assertion */
92 	u32 t_iaa;	/* initial access time */
93 	u32 t_oe;	/* access time from OE assertion */
94 	u32 t_ce;	/* access time from CS asertion */
95 	u32 t_rd_cycle;	/* read cycle time */
100 	u32 t_wpl;	/* write assertion time */
101 	u32 t_wph;	/* write deassertion time */
102 	u32 t_wr_cycle;	/* write cycle time */
106 	u32 t_ces;	/* CS setup time to clk */
107 	u32 t_avds;	/* ADV setup time to clk */
108 	u32 t_avdh;	/* ADV hold time from clk */
109 	u32 t_ach;	/* address hold time from clk */
118 	u8 cyc_aavdh_oe;/* read address hold time in cycles */
119 	u8 cyc_aavdh_we;/* write address hold time in cycles */
120 	u8 cyc_oe;	/* access time from OE assertion in cycles */
121 	u8 cyc_wpl;	/* write deassertion time in cycles */
122 	u32 cyc_iaa;	/* initial access time in cycles */