Lines Matching +full:4 +full:- +full:lane
1 /* SPDX-License-Identifier: GPL-2.0 */
10 * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
13 * MIPI D-PHY phy.
20 * Clock transitions and disable the Clock Lane HS-RX.
30 * send HS clock after the last associated Data Lane has
42 * the transmitter prior to any associated Data Lane beginning
53 * Lane LP-00 Line state immediately before the HS-0 Line
65 * should ignore any Clock Lane HS transitions, starting from
76 * Time, in picoseconds, for the Clock Lane receiver to enable
86 * Time, in picoseconds, that the transmitter drives the HS-0
97 * Time, in picoseconds, that the transmitter drives the HS-0
105 * Time, in picoseconds, for the Data Lane receiver to enable
108 * Maximum value: 35000 ps + 4 * @hs_clk_rate period in ps
116 * of @hs_trail or @clk_trail, to the start of the LP- 11
126 * Time, in picoseconds, that the transmitter drives LP-11
137 * Lane LP-00 Line state immediately before the HS-0 Line
140 * Minimum value: 40000 ps + 4 * @hs_clk_rate period in ps
149 * shall ignore any Data Lane HS transitions, starting from
160 * Time interval, in picoseconds, during which the HS-RX
161 * should ignore any transitions on the Data Lane, following a
163 * beginning of the LP-11 state following the HS burst.
166 * Maximum value: 55000 ps + 4 * @hs_clk_rate period in ps
178 * 60000 ps + 4 * @hs_clk_rate period in ps)
185 * Time, in picoseconds, that the transmitter drives the HS-0
203 * Transmitted length, in picoseconds, of any Low-Power state
214 * Bridge state (LP-00) after accepting control during a Link
225 * Bridge state (LP-00) before releasing control during a Link
228 * Value: 4 * @lpx
236 * the LP-10 state before transmitting the Bridge state
237 * (LP-00) during a Link Turnaround.
247 * Time, in microseconds, that a transmitter drives a Mark-1
258 * Clock rate, in Hertz, of the high-speed clock.
265 * Clock rate, in Hertz, of the low-power clock.
273 * lane 0, used for the transmissions.