Lines Matching +full:0 +full:xf0

19 #define TPS65218			0xF0
22 #define TPS65218_I2C_ID			0x24
25 #define TPS65218_REG_CHIPID		0x00
26 #define TPS65218_REG_INT1		0x01
27 #define TPS65218_REG_INT2		0x02
28 #define TPS65218_REG_INT_MASK1		0x03
29 #define TPS65218_REG_INT_MASK2		0x04
30 #define TPS65218_REG_STATUS		0x05
31 #define TPS65218_REG_CONTROL		0x06
32 #define TPS65218_REG_FLAG		0x07
34 #define TPS65218_REG_PASSWORD		0x10
35 #define TPS65218_REG_ENABLE1		0x11
36 #define TPS65218_REG_ENABLE2		0x12
37 #define TPS65218_REG_CONFIG1		0x13
38 #define TPS65218_REG_CONFIG2		0x14
39 #define TPS65218_REG_CONFIG3		0x15
40 #define TPS65218_REG_CONTROL_DCDC1	0x16
41 #define TPS65218_REG_CONTROL_DCDC2	0x17
42 #define TPS65218_REG_CONTROL_DCDC3	0x18
43 #define TPS65218_REG_CONTROL_DCDC4	0x19
44 #define TPS65218_REG_CONTRL_SLEW_RATE	0x1A
45 #define TPS65218_REG_CONTROL_LDO1	0x1B
46 #define TPS65218_REG_SEQ1		0x20
47 #define TPS65218_REG_SEQ2		0x21
48 #define TPS65218_REG_SEQ3		0x22
49 #define TPS65218_REG_SEQ4		0x23
50 #define TPS65218_REG_SEQ5		0x24
51 #define TPS65218_REG_SEQ6		0x25
52 #define TPS65218_REG_SEQ7		0x26
55 #define TPS65218_CHIPID_CHIP_MASK	0xF8
56 #define TPS65218_CHIPID_REV_MASK	0x07
58 #define TPS65218_REV_1_0		0x0
59 #define TPS65218_REV_1_1		0x1
60 #define TPS65218_REV_2_0		0x2
61 #define TPS65218_REV_2_1		0x3
68 #define TPS65218_INT1_PRGC		BIT(0)
75 #define TPS65218_INT2_LS1_I		BIT(0)
82 #define TPS65218_INT_MASK1_PRGC		BIT(0)
89 #define TPS65218_INT_MASK2_LS1_I	BIT(0)
95 #define TPS65218_STATUS_STATE_MASK	0xC
96 #define TPS65218_STATUS_CC_STAT		0x3
99 #define TPS65218_CONTROL_CC_AQ	BIT(0)
108 #define TPS65218_FLAG_DC1_FLG		BIT(0)
115 #define TPS65218_ENABLE1_DC1_EN		BIT(0)
123 #define TPS65218_ENABLE2_LDO1_EN	BIT(0)
129 #define TPS65218_CONFIG1_PGDLY_MASK	0x18
131 #define TPS65218_CONFIG1_UVLO_MASK	0x3
132 #define TPS65218_CONFIG1_UVLO_2750000	0x0
133 #define TPS65218_CONFIG1_UVLO_2950000	0x1
134 #define TPS65218_CONFIG1_UVLO_3250000	0x2
135 #define TPS65218_CONFIG1_UVLO_3350000	0x3
139 #define TPS65218_CONFIG2_LS3ILIM_MASK	0xC
140 #define TPS65218_CONFIG2_LS2ILIM_MASK	0x3
147 #define TPS65218_CONFIG3_LS1DCHRG	BIT(0)
150 #define TPS65218_CONTROL_DCDC1_MASK	0x7F
153 #define TPS65218_CONTROL_DCDC2_MASK	0x3F
156 #define TPS65218_CONTROL_DCDC3_MASK	0x3F
159 #define TPS65218_CONTROL_DCDC4_MASK	0x3F
163 #define TPS65218_SLEW_RATE_SLEW_MASK	0x7
165 #define TPS65218_CONTROL_LDO1_MASK	0x3F
174 #define TPS65218_SEQ1_DLY1		BIT(0)
177 #define TPS65218_SEQ2_DLY9		BIT(0)
179 #define TPS65218_SEQ3_DC2_SEQ_MASK	0xF0
180 #define TPS65218_SEQ3_DC1_SEQ_MASK	0xF
182 #define TPS65218_SEQ4_DC4_SEQ_MASK	0xF0
183 #define TPS65218_SEQ4_DC3_SEQ_MASK	0xF
185 #define TPS65218_SEQ5_DC6_SEQ_MASK	0xF0
186 #define TPS65218_SEQ5_DC5_SEQ_MASK	0xF
188 #define TPS65218_SEQ6_LS1_SEQ_MASK	0xF0
189 #define TPS65218_SEQ6_LDO1_SEQ_MASK	0xF
191 #define TPS65218_SEQ7_GPO3_SEQ_MASK	0xF0
192 #define TPS65218_SEQ7_GPO1_SEQ_MASK	0xF
193 #define TPS65218_PROTECT_NONE		0