Lines Matching full:x3

26 #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_MASK		(0x3 << 30)
30 #define IMX6Q_GPR0_CLOCK_8_MUX_SEL_SSI3_RX_BIT_CLK	(0x3 << 30)
31 #define IMX6Q_GPR0_CLOCK_0_MUX_SEL_MASK		(0x3 << 28)
35 #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_MASK		(0x3 << 26)
39 #define IMX6Q_GPR0_CLOCK_B_MUX_SEL_SSI3_TX_BIT_CLK	(0x3 << 26)
40 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_MASK		(0x3 << 24)
41 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7_MUXED	(0x3 << 24)
42 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_AUDMUX_RXCLK_P7	(0x3 << 24)
43 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_SSI_SRCK	(0x3 << 24)
44 #define IMX6Q_GPR0_CLOCK_3_MUX_SEL_SSI3_RX_BIT_CLK	(0x3 << 24)
45 #define IMX6Q_GPR0_CLOCK_A_MUX_SEL_MASK		(0x3 << 22)
49 #define IMX6Q_GPR0_CLOCK_A_MUX_SEL_SSI2_TX_BIT_CLK	(0x3 << 22)
50 #define IMX6Q_GPR0_CLOCK_2_MUX_SEL_MASK		(0x3 << 20)
54 #define IMX6Q_GPR0_CLOCK_2_MUX_SEL_SSI2_RX_BIT_CLK	(0x3 << 20)
55 #define IMX6Q_GPR0_CLOCK_9_MUX_SEL_MASK		(0x3 << 18)
59 #define IMX6Q_GPR0_CLOCK_9_MUX_SEL_SSI1_SSI_TX_BIT_CLK	(0x3 << 18)
60 #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_MASK		(0x3 << 16)
64 #define IMX6Q_GPR0_CLOCK_1_MUX_SEL_SSI1_SSI_RX_BIT_CLK	(0x3 << 16)
65 #define IMX6Q_GPR0_TX_CLK2_MUX_SEL_MASK		(0x3 << 14)
94 #define IMX6Q_GPR1_PCIE_REQ_MASK		(0x3 << 30)
124 #define IMX6Q_GPR1_ADDRS3_MASK			(0x3 << 10)
129 #define IMX6Q_GPR1_ADDRS2_MASK			(0x3 << 7)
131 #define IMX6Q_GPR1_ADDRS1_MASK			(0x3 << 4)
133 #define IMX6Q_GPR1_ADDRS0_MASK			(0x3 << 1)
136 #define IMX6Q_GPR2_COUNTER_RESET_VAL_MASK	(0x3 << 20)
140 #define IMX6Q_GPR2_COUNTER_RESET_VAL_6		(0x3 << 20)
145 #define IMX6Q_GPR2_LVDS_CLK_SHIFT_3		(0x3 << 16)
172 #define IMX6Q_GPR2_CH1_MODE_MASK		(0x3 << 2)
175 #define IMX6Q_GPR2_CH1_MODE_EN_ROUTE_DI1	(0x3 << 2)
176 #define IMX6Q_GPR2_CH0_MODE_MASK		(0x3 << 0)
179 #define IMX6Q_GPR2_CH0_MODE_EN_ROUTE_DI1	(0x3 << 0)
181 #define IMX6Q_GPR3_GPU_DBG_MASK			(0x3 << 29)
198 #define IMX6Q_GPR3_LVDS1_MUX_CTL_MASK		(0x3 << 8)
202 #define IMX6Q_GPR3_LVDS1_MUX_CTL_IPU2_DI1	(0x3 << 8)
203 #define IMX6Q_GPR3_LVDS0_MUX_CTL_MASK		(0x3 << 6)
207 #define IMX6Q_GPR3_LVDS0_MUX_CTL_IPU2_DI1	(0x3 << 6)
209 #define IMX6Q_GPR3_MIPI_MUX_CTL_MASK		(0x3 << 4)
213 #define IMX6Q_GPR3_MIPI_MUX_CTL_IPU2_DI1	(0x3 << 4)
215 #define IMX6Q_GPR3_HDMI_MUX_CTL_MASK		(0x3 << 2)
219 #define IMX6Q_GPR3_HDMI_MUX_CTL_IPU2_DI1	(0x3 << 2)
278 #define IMX6Q_GPR10_LOCK_DCIC2_MUX_MASK		(0x3 << 18)
279 #define IMX6Q_GPR10_LOCK_DCIC1_MUX_MASK		(0x3 << 16)
287 #define IMX6Q_GPR10_DCIC2_MUX_CTL_MASK		(0x3 << 2)
291 #define IMX6Q_GPR10_DCIC2_MUX_CTL_IPU2_DI1	(0x3 << 2)
292 #define IMX6Q_GPR10_DCIC1_MUX_CTL_MASK		(0x3 << 0)
296 #define IMX6Q_GPR10_DCIC1_MUX_CTL_IPU2_DI1	(0x3 << 0)
314 #define IMX6Q_GPR13_SATA_RX_EQ_VAL_2_0_DB	(0x3 << 24)
330 #define IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F	(0x3 << 16)
339 #define IMX6Q_GPR13_SATA_TX_ATTEN_10_16		(0x3 << 11)
346 #define IMX6Q_GPR13_SATA_TX_BOOST_1_11_DB	(0x3 << 7)
396 #define IMX6SL_GPR1_FEC_CLOCK_MUX1_SEL_MASK    (0x3 << 17)
406 #define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_MASK		(0x3 << 13)
407 #define IMX6SX_GPR1_FEC_CLOCK_PAD_DIR_MASK		(0x3 << 17)
408 #define IMX6SX_GPR1_FEC_CLOCK_MUX_SEL_EXT		(0x3 << 13)
426 #define IMX6SX_GPR5_CSI2_MUX_CTRL_MASK			(0x3 << 27)
430 #define IMX6SX_GPR5_CSI2_MUX_CTRL_GND			(0x3 << 27)
435 #define IMX6SX_GPR5_CSI1_MUX_CTRL_MASK			(0x3 << 4)
439 #define IMX6SX_GPR5_CSI1_MUX_CTRL_GND			(0x3 << 4)
460 #define IMX6UL_GPR1_ENET_CLK_DIR		(0x3 << 17)
461 #define IMX6UL_GPR1_ENET_CLK_OUTPUT		(0x3 << 17)