linux/mfd/stm32-timers.h

1 /* SPDX-License-Identifier: GPL-2.0 */
12 #include <linux/dma-mapping.h>
21 #define TIM_CCMR1	0x18			/* Capt/Comp 1 Mode Reg			*/
22 #define TIM_CCMR2	0x1C			/* Capt/Comp 2 Mode Reg			*/
23 #define TIM_CCER	0x20			/* Capt/Comp Enable Reg			*/
26 #define TIM_ARR		0x2c			/* Auto-Reload Register			*/
27 #define TIM_CCRx(x)	(0x34 + 4 * ((x) - 1))	/* Capt/Comp Register x (x ∈ {1, .. 4})	*/
28 #define TIM_CCR1	TIM_CCRx(1)		/* Capt/Comp Register 1			*/
29 #define TIM_CCR2	TIM_CCRx(2)		/* Capt/Comp Register 2			*/
30 #define TIM_CCR3	TIM_CCRx(3)		/* Capt/Comp Register 3			*/
31 #define TIM_CCR4	TIM_CCRx(4)		/* Capt/Comp Register 4			*/
32 #define TIM_BDTR	0x44			/* Break and Dead-Time Reg		*/
39 #define TIM_CR1_ARPE		BIT(7)					/* Auto-reload Preload Ena			*/
45 #define TIM_DIER_CCxIE(x)	BIT(1 + ((x) - 1))			/* CCx Interrupt Enable	(x ∈ {1, .. 4})		*/
51 #define TIM_DIER_CCxDE(x)	BIT(9 + ((x) - 1))			/* CCx DMA request Enable (x ∈ {1, .. 4})	*/
75 #define TIM_CCER_CCxE(x)	BIT(0 + 4 * ((x) - 1))			/* Capt/Comp x  out Ena (x ∈ {1, .. 4})		*/
76 #define TIM_CCER_CCxP(x)	BIT(1 + 4 * ((x) - 1))			/* Capt/Comp x  Polarity (x ∈ {1, .. 4})	*/
77 #define TIM_CCER_CCxNE(x)	BIT(2 + 4 * ((x) - 1))			/* Capt/Comp xN out Ena (x ∈ {1, .. 4})		*/
78 #define TIM_CCER_CCxNP(x)	BIT(3 + 4 * ((x) - 1))			/* Capt/Comp xN Polarity (x ∈ {1, .. 4})	*/
79 #define TIM_CCER_CC1E		TIM_CCER_CCxE(1)			/* Capt/Comp 1  out Ena				*/
80 #define TIM_CCER_CC1P		TIM_CCER_CCxP(1)			/* Capt/Comp 1  Polarity			*/
81 #define TIM_CCER_CC1NE		TIM_CCER_CCxNE(1)			/* Capt/Comp 1N out Ena				*/
82 #define TIM_CCER_CC1NP		TIM_CCER_CCxNP(1)			/* Capt/Comp 1N Polarity			*/
83 #define TIM_CCER_CC2E		TIM_CCER_CCxE(2)			/* Capt/Comp 2  out Ena				*/
84 #define TIM_CCER_CC2P		TIM_CCER_CCxP(2)			/* Capt/Comp 2  Polarity			*/
85 #define TIM_CCER_CC2NE		TIM_CCER_CCxNE(2)			/* Capt/Comp 2N out Ena				*/
86 #define TIM_CCER_CC2NP		TIM_CCER_CCxNP(2)			/* Capt/Comp 2N Polarity			*/
87 #define TIM_CCER_CC3E		TIM_CCER_CCxE(3)			/* Capt/Comp 3  out Ena				*/
88 #define TIM_CCER_CC3P		TIM_CCER_CCxP(3)			/* Capt/Comp 3  Polarity			*/
89 #define TIM_CCER_CC3NE		TIM_CCER_CCxNE(3)			/* Capt/Comp 3N out Ena				*/
90 #define TIM_CCER_CC3NP		TIM_CCER_CCxNP(3)			/* Capt/Comp 3N Polarity			*/
91 #define TIM_CCER_CC4E		TIM_CCER_CCxE(4)			/* Capt/Comp 4  out Ena				*/
92 #define TIM_CCER_CC4P		TIM_CCER_CCxP(4)			/* Capt/Comp 4  Polarity			*/
93 #define TIM_CCER_CC4NE		TIM_CCER_CCxNE(4)			/* Capt/Comp 4N out Ena				*/
94 #define TIM_CCER_CC4NP		TIM_CCER_CCxNP(4)			/* Capt/Comp 4N Polarity			*/
137  * struct stm32_timers_dma - STM32 timer DMA handling.
157 	unsigned int nr_irqs;
158 	int irq[STM32_TIMERS_MAX_IRQS];
162 int stm32_timers_dma_burst_read(struct device *dev, u32 *buf,
164 				unsigned int num_reg, unsigned int bursts,
167 static inline int stm32_timers_dma_burst_read(struct device *dev, u32 *buf,  in stm32_timers_dma_burst_read()
170 					      unsigned int num_reg,  in stm32_timers_dma_burst_read()
171 					      unsigned int bursts,  in stm32_timers_dma_burst_read()
174 	return -ENODEV;  in stm32_timers_dma_burst_read()