Lines Matching +full:0 +full:x5c
7 #define BD96801_REG_SSCG_CTRL 0x09
8 #define BD96801_REG_SHD_INTB 0x20
9 #define BD96801_LDO5_VOL_LVL_REG 0x2c
10 #define BD96801_LDO6_VOL_LVL_REG 0x2d
11 #define BD96801_LDO7_VOL_LVL_REG 0x2e
12 #define BD96801_REG_BUCK_OVP 0x30
13 #define BD96801_REG_BUCK_OVD 0x35
14 #define BD96801_REG_LDO_OVP 0x31
15 #define BD96801_REG_LDO_OVD 0x36
16 #define BD96801_REG_BOOT_OVERTIME 0x3a
17 #define BD96801_REG_WD_TMO 0x40
18 #define BD96801_REG_WD_CONF 0x41
19 #define BD96801_REG_WD_FEED 0x42
20 #define BD96801_REG_WD_FAILCOUNT 0x43
21 #define BD96801_REG_WD_ASK 0x46
22 #define BD96801_REG_WD_STATUS 0x4a
23 #define BD96801_REG_PMIC_STATE 0x4f
24 #define BD96801_REG_EXT_STATE 0x50
26 #define BD96801_STATE_STBY 0x09
28 #define BD96801_LOCK_REG 0x04
29 #define BD96801_UNLOCK 0x9d
30 #define BD96801_LOCK 0x00
33 #define BD96801_REG_INT_MAIN 0x51
38 * The 'main status register' is located at 0x51.
39 * The ERRB status registers are located at 0x52 ... 0x5B
40 * INTB status registers are at range 0x5c ... 0x63
42 #define BD96801_REG_INT_SYS_ERRB1 0x52
43 #define BD96801_REG_INT_SYS_INTB 0x5c
44 #define BD96801_REG_INT_LDO7_INTB 0x63
47 #define BD96801_REG_MASK_SYS_INTB 0x73
48 #define BD96801_REG_MASK_SYS_ERRB 0x69
50 #define BD96801_MAX_REGISTER 0x7a
52 #define BD96801_OTP_ERR_MASK BIT(0)
60 #define BD96801_VREF_ERR_MASK BIT(0)
68 #define BD96801_INT_PRSTB_WDT_ERR_MASK BIT(0)
71 #define BD96801_OUT_PVIN_ERR_MASK BIT(0)
78 /* Reg 0x52, 0x53, 0x54 - ERRB system IRQs */
99 /* Reg 0x55 BUCK1 ERR IRQs */
105 /* Reg 0x56 BUCK2 ERR IRQs */
111 /* Reg 0x57 BUCK3 ERR IRQs */
117 /* Reg 0x58 BUCK4 ERR IRQs */
123 /* Reg 0x59 LDO5 ERR IRQs */
129 /* Reg 0x5a LDO6 ERR IRQs */
135 /* Reg 0x5b LDO7 ERR IRQs */
144 /* Reg 0x5c (System INTB) */
150 /* Reg 0x5d (BUCK1 INTB) */
158 /* Reg 0x5e (BUCK2 INTB) */
166 /* Reg 0x5f (BUCK3 INTB)*/
174 /* Reg 0x60 (BUCK4 INTB)*/
182 /* Reg 0x61 (LDO5 INTB) */
183 BD96801_LDO5_OCPH_STAT, /* bit [0] */
187 /* Reg 0x62 (LDO6 INTB) */
188 BD96801_LDO6_OCPH_STAT, /* bit [0] */
192 /* Reg 0x63 (LDO7 INTB) */
193 BD96801_LDO7_OCPH_STAT, /* bit [0] */
199 #define BD96801_TW_STAT_MASK BIT(0)
204 #define BD96801_BUCK_OCPH_STAT_MASK BIT(0)
211 #define BD96801_LDO_OCPH_STAT_MASK BIT(0)