Lines Matching +full:4 +full:- +full:bits

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
9  * Author: yanglsh@embest-tech.com
32 	/* LDO for Low-Power State Retention */
229 /* BD71815_REG_BUCK1_MODE bits */
236 #define BD71815_BUCK_PWM_FIXED			BIT(4)
242 /* BD71815_REG_BUCK1_VOLT_H bits */
249 /* BD71815_REG_BUCK2_VOLT_H bits */
256 /* LED enable bits at LED_CTRL reg */
257 #define LED_CHGDONE_EN				BIT(4)
262 /* BD71815_REG_LDO1_CTRL bits */
267 #define VOSNVS_SW_EN				BIT(4)
273 #define LDO1_SUSP_ON				BIT(4)
287 #define LDO3_SUSP_ON				BIT(4)
298 #define LDO5_SUSP_ON				BIT(4)
308 #define DVREF_SUSP_ON				BIT(4)
314 /* BD71815_REG_OUT32K bits */
320 /* BD71815_REG_BAT_STAT bits */
323 #define BAT_DET_DONE				BIT(4)
327 /* BD71815_REG_VBUS_STAT bits */
333 /* BD71815_REG_ALM0_MASK bits */
336 /* BD71815_REG_INT_EN_00 bits */
339 /* BD71815_REG_INT_STAT_03 bits */
344 #define POWERON_SHORT				BIT(4)
347 /* BD71805_REG_INT_STAT_08 bits */
351 /* BD71805_REG_INT_STAT_11 bits */
355 #define	INT_STAT_11_VF125_RES			BIT(4)
364 /* BD71815_REG_PWRCTRL bits */
367 /* BD71815_REG_GPO bits */
369 #define BD71815_GPIO_DRIVE_MASK			BIT(4)
371 #define BD71815_GPIO_CMOS			BIT(4)
445 	/* Battery Mon 4 INT_STAT_10 */
471 #define BD71815_INT_BUCK5_OCP_MASK			BIT(4)
479 #define BD71815_INT_DCIN_OVP_RES_MASK			BIT(4)
495 #define BD71815_INT_CHG_RECHARGE_RES_MASK		BIT(4)
502 #define BD71815_INT_BAT_REMOVED_MASK			BIT(4)
510 #define BD71815_INT_BAT_LOW_VOLT_RES_MASK		BIT(4)
526 #define BD71815_INT_BAT_OVER_CURR_3_RES_MASK		BIT(4)
533 #define BD71815_INT_TEMP_CHIP_OVER_125_RES_MASK		BIT(4)
542 /* BD71815_REG_CC_CTRL bits */
553 /* BD71815_REG_REX_CTRL_1 bits */
554 #define REX_CLR						BIT(4)
556 /* BD71815_REG_REX_CTRL_1 bits */
559 /* BD71815_REG_LED_CTRL bits */
560 #define CHGDONE_LED_EN					BIT(4)