Lines Matching +full:2 +full:- +full:wire
1 /* SPDX-License-Identifier: GPL-2.0-only */
6 * Copyright (C) 2007-2009 Motorola, Inc.
30 #define CPCAP_REG_INT2 0x0004 /* Interrupt 2 */
34 #define CPCAP_REG_INTM2 0x0014 /* Interrupt Mask 2 */
38 #define CPCAP_REG_INTS2 0x0024 /* Interrupt Sense 2 */
42 #define CPCAP_REG_ASSIGN2 0x0034 /* Resource Assignment 2 */
48 #define CPCAP_REG_VERSC2 0x004c /* Version Control 2 */
52 #define CPCAP_REG_MI2 0x0208 /* Macro Interrupt 2 */
53 #define CPCAP_REG_MIM2 0x020c /* Macro Interrupt Mask 2 */
55 #define CPCAP_REG_UCC2 0x0214 /* UC Control 2 */
58 #define CPCAP_REG_PC2 0x0220 /* Power Cut 2 */
62 #define CPCAP_REG_MT2 0x0230 /* Memory Transfer 2 */
68 #define CPCAP_REG_SW2 0x0408 /* Stop Watch 2 */
71 #define CPCAP_REG_TOD2 0x0414 /* Time of Day 2 */
73 #define CPCAP_REG_TODA2 0x041c /* Time of Day Alarm 2 */
77 #define CPCAP_REG_VAL2 0x042c /* Validity 2 */
81 #define CPCAP_REG_Si2CC2 0x0608 /* Switcher I2C Control 2 */
83 #define CPCAP_REG_S1C2 0x0610 /* Switcher 1 Control 2 */
84 #define CPCAP_REG_S2C1 0x0614 /* Switcher 2 Control 1 */
85 #define CPCAP_REG_S2C2 0x0618 /* Switcher 2 Control 2 */
88 #define CPCAP_REG_S4C2 0x0624 /* Switcher 4 Control 2 */
111 #define CPCAP_REG_URM2 0x0680 /* Useroff Regulator Mask 2 */
128 #define CPCAP_REG_MIPIS2 0x083c /* MIPI Slimbus 2 */
134 #define CPCAP_REG_CCCC2 0x0a08 /* Coincell and Coulomb Ctr Ctrl 2 */
136 #define CPCAP_REG_CCS2 0x0a10 /* Coulomb Counter Sample 2 */
138 #define CPCAP_REG_CCA2 0x0a18 /* Coulomb Counter Accumulator 2 */
144 #define CPCAP_REG_ADCC2 0x0c04 /* A/D Converter Configuration 2 */
147 #define CPCAP_REG_ADCD2 0x0c10 /* A/D Converter Data 2 */
154 #define CPCAP_REG_ADCAL2 0x0c2c /* A/D Converter Calibration 2 */
157 #define CPCAP_REG_USBC2 0x0e04 /* USB Control 2 */
164 #define CPCAP_REG_UFC2 0x0e20 /* ULPI Function Control 2 */
167 #define CPCAP_REG_UIC2 0x0e2c /* ULPI Interface Control 2 */
170 #define CPCAP_REG_USBOTG2 0x0e38 /* USB OTG Control 2 */
173 #define CPCAP_REG_UIER2 0x0e44 /* USB Interrupt Enable Rising 2 */
182 #define CPCAP_REG_SCR2 0x0e68 /* Scratch 2 */
186 #define CPCAP_REG_OWDC 0x0eb0 /* One Wire Device Control */
191 #define CPCAP_REG_GPIO2 0x0ec4 /* GPIO 2 Control */
212 #define CPCAP_REG_OW1C 0x1200 /* One Wire 1 Command */
213 #define CPCAP_REG_OW1D 0x1204 /* One Wire 1 Data */
214 #define CPCAP_REG_OW1I 0x1208 /* One Wire 1 Interrupt */
215 #define CPCAP_REG_OW1IE 0x120c /* One Wire 1 Interrupt Enable */
217 #define CPCAP_REG_OW1 0x1214 /* One Wire 1 Control */
219 #define CPCAP_REG_OW2C 0x1220 /* One Wire 2 Command */
220 #define CPCAP_REG_OW2D 0x1224 /* One Wire 2 Data */
221 #define CPCAP_REG_OW2I 0x1228 /* One Wire 2 Interrupt */
222 #define CPCAP_REG_OW2IE 0x122c /* One Wire 2 Interrupt Enable */
224 #define CPCAP_REG_OW2 0x1234 /* One Wire 2 Control */
226 #define CPCAP_REG_OW3C 0x1240 /* One Wire 3 Command */
227 #define CPCAP_REG_OW3D 0x1244 /* One Wire 3 Data */
228 #define CPCAP_REG_OW3I 0x1248 /* One Wire 3 Interrupt */
229 #define CPCAP_REG_OW3IE 0x124c /* One Wire 3 Interrupt Enable */
231 #define CPCAP_REG_OW3 0x1254 /* One Wire 3 Control */
235 #define CPCAP_REG_LGPU 0x1264 /* LMR GCAI GPIO Pull-up */