linux/mfd/motorola-cpcap.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
6  * Copyright (C) 2007-2009 Motorola, Inc.
18 #define CPCAP_VENDOR_TI		1
20 #define CPCAP_REVISION_MAJOR(r)	(((r) >> 4) + 1)
29 #define CPCAP_REG_INT1		0x0000	/* Interrupt 1 */
33 #define CPCAP_REG_INTM1		0x0010	/* Interrupt Mask 1 */
37 #define CPCAP_REG_INTS1		0x0020	/* Interrupt Sense 1 */
41 #define CPCAP_REG_ASSIGN1	0x0030	/* Resource Assignment 1 */
47 #define CPCAP_REG_VERSC1	0x0048	/* Version Control 1 */
50 #define CPCAP_REG_MI1		0x0200	/* Macro Interrupt 1 */
51 #define CPCAP_REG_MIM1		0x0204	/* Macro Interrupt Mask 1 */
54 #define CPCAP_REG_UCC1		0x0210	/* UC Control 1 */
57 #define CPCAP_REG_PC1		0x021c	/* Power Cut 1 */
61 #define CPCAP_REG_MT1		0x022c	/* Memory Transfer 1 */
67 #define CPCAP_REG_SW1		0x0404	/* Stop Watch 1 */
70 #define CPCAP_REG_TOD1		0x0410	/* Time of Day 1 */
72 #define CPCAP_REG_TODA1		0x0418	/* Time of Day Alarm 1 */
76 #define CPCAP_REG_VAL1		0x0428	/* Validity 1 */
80 #define CPCAP_REG_SI2CC1	0x0604	/* Switcher I2C Control 1 */
82 #define CPCAP_REG_S1C1		0x060c	/* Switcher 1 Control 1 */
83 #define CPCAP_REG_S1C2		0x0610	/* Switcher 1 Control 2 */
84 #define CPCAP_REG_S2C1		0x0614	/* Switcher 2 Control 1 */
87 #define CPCAP_REG_S4C1		0x0620	/* Switcher 4 Control 1 */
110 #define CPCAP_REG_URM1		0x067c	/* Useroff Regulator Mask 1 */
127 #define CPCAP_REG_MIPIS1	0x0838	/* MIPI Slimbus 1 */
132 #define CPCAP_REG_CCC1		0x0a00	/* Coulomb Counter Control 1 */
135 #define CPCAP_REG_CCS1		0x0a0c	/* Coulomb Counter Sample 1 */
137 #define CPCAP_REG_CCA1		0x0a14	/* Coulomb Counter Accumulator 1 */
143 #define CPCAP_REG_ADCC1		0x0c00	/* A/D Converter Configuration 1 */
146 #define CPCAP_REG_ADCD1		0x0c0c	/* A/D Converter Data 1 */
153 #define CPCAP_REG_ADCAL1	0x0c28	/* A/D Converter Calibration 1 */
156 #define CPCAP_REG_USBC1		0x0e00	/* USB Control 1 */
163 #define CPCAP_REG_UFC1		0x0e1c	/* ULPI Function Control 1 */
166 #define CPCAP_REG_UIC1		0x0e28	/* ULPI Interface Control 1 */
169 #define CPCAP_REG_USBOTG1	0x0e34	/* USB OTG Control 1 */
172 #define CPCAP_REG_UIER1		0x0e40	/* USB Interrupt Enable Rising 1 */
175 #define CPCAP_REG_UIEF1		0x0e4c	/* USB Interrupt Enable Falling 1 */
176 #define CPCAP_REG_UIEF2		0x0e50	/* USB Interrupt Enable Falling 1 */
177 #define CPCAP_REG_UIEF3		0x0e54	/* USB Interrupt Enable Falling 1 */
181 #define CPCAP_REG_SCR1		0x0e64	/* Scratch 1 */
186 #define CPCAP_REG_OWDC		0x0eb0	/* One Wire Device Control */
189 #define CPCAP_REG_GPIO1		0x0ebc	/* GPIO 1 Control */
212 #define CPCAP_REG_OW1C		0x1200	/* One Wire 1 Command */
213 #define CPCAP_REG_OW1D		0x1204	/* One Wire 1 Data */
214 #define CPCAP_REG_OW1I		0x1208	/* One Wire 1 Interrupt */
215 #define CPCAP_REG_OW1IE		0x120c	/* One Wire 1 Interrupt Enable */
217 #define CPCAP_REG_OW1		0x1214	/* One Wire 1 Control */
219 #define CPCAP_REG_OW2C		0x1220	/* One Wire 2 Command */
220 #define CPCAP_REG_OW2D		0x1224	/* One Wire 2 Data */
221 #define CPCAP_REG_OW2I		0x1228	/* One Wire 2 Interrupt */
222 #define CPCAP_REG_OW2IE		0x122c	/* One Wire 2 Interrupt Enable */
224 #define CPCAP_REG_OW2		0x1234	/* One Wire 2 Control */
226 #define CPCAP_REG_OW3C		0x1240	/* One Wire 3 Command */
227 #define CPCAP_REG_OW3D		0x1244	/* One Wire 3 Data */
228 #define CPCAP_REG_OW3I		0x1248	/* One Wire 3 Interrupt */
229 #define CPCAP_REG_OW3IE		0x124c	/* One Wire 3 Interrupt Enable */
231 #define CPCAP_REG_OW3		0x1254	/* One Wire 3 Control */
235 #define CPCAP_REG_LGPU		0x1264	/* LMR GCAI GPIO Pull-up */