Lines Matching +full:0 +full:x4a
16 #define I2C_ADDR_PMIC (0x46 >> 1)
17 #define I2C_ADDR_MUIC (0x4A >> 1)
18 #define I2C_ADDR_FG (0x6C >> 1)
21 MAXIM_DEVICE_TYPE_UNKNOWN = 0,
28 /* Slave addr = 0x4A: MUIC and Charger */
30 MAX14577_REG_DEVICEID = 0x00,
31 MAX14577_REG_INT1 = 0x01,
32 MAX14577_REG_INT2 = 0x02,
33 MAX14577_REG_INT3 = 0x03,
34 MAX14577_REG_STATUS1 = 0x04,
35 MAX14577_REG_STATUS2 = 0x05,
36 MAX14577_REG_STATUS3 = 0x06,
37 MAX14577_REG_INTMASK1 = 0x07,
38 MAX14577_REG_INTMASK2 = 0x08,
39 MAX14577_REG_INTMASK3 = 0x09,
40 MAX14577_REG_CDETCTRL1 = 0x0A,
41 MAX14577_REG_RFU = 0x0B,
42 MAX14577_REG_CONTROL1 = 0x0C,
43 MAX14577_REG_CONTROL2 = 0x0D,
44 MAX14577_REG_CONTROL3 = 0x0E,
45 MAX14577_REG_CHGCTRL1 = 0x0F,
46 MAX14577_REG_CHGCTRL2 = 0x10,
47 MAX14577_REG_CHGCTRL3 = 0x11,
48 MAX14577_REG_CHGCTRL4 = 0x12,
49 MAX14577_REG_CHGCTRL5 = 0x13,
50 MAX14577_REG_CHGCTRL6 = 0x14,
51 MAX14577_REG_CHGCTRL7 = 0x15,
56 /* Slave addr = 0x4A: MUIC */
58 MAX14577_MUIC_REG_STATUS1 = 0x04,
59 MAX14577_MUIC_REG_STATUS2 = 0x05,
60 MAX14577_MUIC_REG_CONTROL1 = 0x0C,
61 MAX14577_MUIC_REG_CONTROL3 = 0x0E,
72 * These values are just a register value bitwise OR with 0x8.
75 MAX14577_CHARGER_TYPE_NONE = 0x0,
76 MAX14577_CHARGER_TYPE_USB = 0x1,
77 MAX14577_CHARGER_TYPE_DOWNSTREAM_PORT = 0x2,
78 MAX14577_CHARGER_TYPE_DEDICATED_CHG = 0x3,
79 MAX14577_CHARGER_TYPE_SPECIAL_500MA = 0x4,
81 MAX14577_CHARGER_TYPE_SPECIAL_1A = 0x5,
83 MAX14577_CHARGER_TYPE_RESERVED = 0x6,
85 MAX14577_CHARGER_TYPE_DEAD_BATTERY = 0x7,
88 * matches register value of 0x6
90 MAX77836_CHARGER_TYPE_SPECIAL_BIAS = 0xe,
91 /* max77836: reserved, register value 0x7 */
92 MAX77836_CHARGER_TYPE_RESERVED = 0xf,
96 #define MAX14577_INT1_ADC_MASK BIT(0)
101 #define MAX14577_INT2_CHGTYP_MASK BIT(0)
108 #define MAX14577_INT3_EOC_MASK BIT(0)
114 #define DEVID_VENDORID_SHIFT 0
116 #define DEVID_VENDORID_MASK (0x07 << DEVID_VENDORID_SHIFT)
117 #define DEVID_DEVICEID_MASK (0x1f << DEVID_DEVICEID_SHIFT)
120 #define STATUS1_ADC_SHIFT 0
124 #define STATUS1_ADC_MASK (0x1f << STATUS1_ADC_SHIFT)
130 #define STATUS2_CHGTYP_SHIFT 0
137 #define STATUS2_CHGTYP_MASK (0x7 << STATUS2_CHGTYP_SHIFT)
146 #define COMN1SW_SHIFT 0
150 #define COMN1SW_MASK (0x7 << COMN1SW_SHIFT)
151 #define COMP2SW_MASK (0x7 << COMP2SW_SHIFT)
161 #define CTRL1_SW_OPEN ((0 << COMP2SW_SHIFT) \
162 | (0 << COMN1SW_SHIFT))
165 #define CTRL2_LOWPWR_SHIFT (0)
183 (0 << CTRL2_LOWPWR_SHIFT))
184 #define CTRL2_CPEN0_LOWPWR1 ((0 << CTRL2_CPEN_SHIFT) | \
188 #define CTRL3_JIGSET_SHIFT 0
192 #define CTRL3_JIGSET_MASK (0x3 << CTRL3_JIGSET_SHIFT)
193 #define CTRL3_BOOTSET_MASK (0x3 << CTRL3_BOOTSET_SHIFT)
194 #define CTRL3_ADCDBSET_MASK (0x3 << CTRL3_ADCDBSET_SHIFT)
195 #define CTRL3_WBTH_MASK (0x3 << CTRL3_WBTH_SHIFT)
197 /* Slave addr = 0x4A: Charger */
199 MAX14577_CHG_REG_STATUS3 = 0x06,
200 MAX14577_CHG_REG_CHG_CTRL1 = 0x0F,
201 MAX14577_CHG_REG_CHG_CTRL2 = 0x10,
202 MAX14577_CHG_REG_CHG_CTRL3 = 0x11,
203 MAX14577_CHG_REG_CHG_CTRL4 = 0x12,
204 MAX14577_CHG_REG_CHG_CTRL5 = 0x13,
205 MAX14577_CHG_REG_CHG_CTRL6 = 0x14,
206 MAX14577_CHG_REG_CHG_CTRL7 = 0x15,
212 #define STATUS3_EOC_SHIFT 0
216 #define STATUS3_EOC_MASK (0x1 << STATUS3_EOC_SHIFT)
217 #define STATUS3_CGMBC_MASK (0x1 << STATUS3_CGMBC_SHIFT)
218 #define STATUS3_OVP_MASK (0x1 << STATUS3_OVP_SHIFT)
219 #define STATUS3_MBCCHGERR_MASK (0x1 << STATUS3_MBCCHGERR_SHIFT)
222 #define CDETCTRL1_CHGDETEN_SHIFT 0
245 #define CHGCTRL1_TCHW_MASK (0x7 << CHGCTRL1_TCHW_SHIFT)
254 #define CHGCTRL3_MBCCVWRC_SHIFT 0
255 #define CHGCTRL3_MBCCVWRC_MASK (0xf << CHGCTRL3_MBCCVWRC_SHIFT)
258 #define CHGCTRL4_MBCICHWRCH_SHIFT 0
259 #define CHGCTRL4_MBCICHWRCH_MASK (0xf << CHGCTRL4_MBCICHWRCH_SHIFT)
264 #define CHGCTRL5_EOCS_SHIFT 0
265 #define CHGCTRL5_EOCS_MASK (0xf << CHGCTRL5_EOCS_SHIFT)
272 #define CHGCTRL7_OTPCGHCVS_SHIFT 0
273 #define CHGCTRL7_OTPCGHCVS_MASK (0x3 << CHGCTRL7_OTPCGHCVS_SHIFT)
315 /* Slave addr = 0x46: PMIC */
317 MAX77836_PMIC_REG_PMIC_ID = 0x20,
318 MAX77836_PMIC_REG_PMIC_REV = 0x21,
319 MAX77836_PMIC_REG_INTSRC = 0x22,
320 MAX77836_PMIC_REG_INTSRC_MASK = 0x23,
321 MAX77836_PMIC_REG_TOPSYS_INT = 0x24,
322 MAX77836_PMIC_REG_TOPSYS_INT_MASK = 0x26,
323 MAX77836_PMIC_REG_TOPSYS_STAT = 0x28,
324 MAX77836_PMIC_REG_MRSTB_CNTL = 0x2A,
325 MAX77836_PMIC_REG_LSCNFG = 0x2B,
327 MAX77836_LDO_REG_CNFG1_LDO1 = 0x51,
328 MAX77836_LDO_REG_CNFG2_LDO1 = 0x52,
329 MAX77836_LDO_REG_CNFG1_LDO2 = 0x53,
330 MAX77836_LDO_REG_CNFG2_LDO2 = 0x54,
331 MAX77836_LDO_REG_CNFG_LDO_BIAS = 0x55,
333 MAX77836_COMP_REG_COMP1 = 0x60,
344 #define MAX77836_TOPSYS_INT_T120C_SHIFT 0
351 #define MAX77836_CNFG1_LDO_TV_SHIFT 0
352 #define MAX77836_CNFG1_LDO_PWRMD_MASK (0x3 << MAX77836_CNFG1_LDO_PWRMD_SHIFT)
353 #define MAX77836_CNFG1_LDO_TV_MASK (0x3f << MAX77836_CNFG1_LDO_TV_SHIFT)
361 #define MAX77836_CNFG2_LDO_SS_SHIFT 0
364 #define MAX77836_CNFG2_LDO_COMP_MASK (0x3 << MAX77836_CNFG2_LDO_COMP_SHIFT)
369 /* Slave addr = 0x6C: Fuel-Gauge/Battery */
371 MAX77836_FG_REG_VCELL_MSB = 0x02,
372 MAX77836_FG_REG_VCELL_LSB = 0x03,
373 MAX77836_FG_REG_SOC_MSB = 0x04,
374 MAX77836_FG_REG_SOC_LSB = 0x05,
375 MAX77836_FG_REG_MODE_H = 0x06,
376 MAX77836_FG_REG_MODE_L = 0x07,
377 MAX77836_FG_REG_VERSION_MSB = 0x08,
378 MAX77836_FG_REG_VERSION_LSB = 0x09,
379 MAX77836_FG_REG_HIBRT_H = 0x0A,
380 MAX77836_FG_REG_HIBRT_L = 0x0B,
381 MAX77836_FG_REG_CONFIG_H = 0x0C,
382 MAX77836_FG_REG_CONFIG_L = 0x0D,
383 MAX77836_FG_REG_VALRT_MIN = 0x14,
384 MAX77836_FG_REG_VALRT_MAX = 0x15,
385 MAX77836_FG_REG_CRATE_MSB = 0x16,
386 MAX77836_FG_REG_CRATE_LSB = 0x17,
387 MAX77836_FG_REG_VRESET = 0x18,
388 MAX77836_FG_REG_FGID = 0x19,
389 MAX77836_FG_REG_STATUS_H = 0x1A,
390 MAX77836_FG_REG_STATUS_L = 0x1B,
429 struct i2c_client *i2c; /* Slave addr = 0x4A */
430 struct i2c_client *i2c_pmic; /* Slave addr = 0x46 */