Lines Matching +full:bit +full:- +full:per +full:- +full:mux

1 /* SPDX-License-Identifier: GPL-2.0 */
5  * Copyright (C) 2018-2020 Intel Corporation, Inc.
55 #define DRBL_RSU_REQUEST		BIT(0)
59 #define DRBL_PKVL_EEPROM_LOAD_SEC	BIT(24)
60 #define DRBL_PKVL1_POLL_EN		BIT(25)
61 #define DRBL_PKVL2_POLL_EN		BIT(26)
62 #define DRBL_CONFIG_SEL			BIT(28)
63 #define DRBL_REBOOT_REQ			BIT(29)
64 #define DRBL_REBOOT_DISABLED		BIT(30)
126 /* Address of 4KB inverted bit vector containing staging area FLASH count */
164 #define get_flash_mux(mux)			FIELD_GET(M10BMC_N6000_FLASH_MUX_SELECTION, mux)  argument
166 #define M10BMC_N6000_FLASH_NIOS_REQUEST		BIT(4)
167 #define M10BMC_N6000_FLASH_HOST_REQUEST		BIT(5)
170 #define M10BMC_N6000_FLASH_WR_MODE		BIT(0)
171 #define M10BMC_N6000_FLASH_RD_MODE		BIT(1)
172 #define M10BMC_N6000_FLASH_BUSY			BIT(2)
188  * struct m10bmc_csr_map - Intel MAX 10 BMC CSR register map
212  * struct intel_m10bmc_platform_info - Intel MAX 10 BMC platform specific information
230  * struct intel_m10bmc_flash_bulk_ops - device specific operations for flash R/W
237  * is locked, @read returns -EBUSY.
254  * struct intel_m10bmc - Intel MAX 10 BMC parent driver data structure
275  * m10bmc_raw_read - read m10bmc register per addr
276  * m10bmc_sys_read - read m10bmc system register per offset
277  * m10bmc_sys_update_bits - update m10bmc system register per offset
285 	ret = regmap_read(m10bmc->regmap, addr, val);  in m10bmc_raw_read()
287 		dev_err(m10bmc->dev, "fail to read raw reg %x: %d\n",  in m10bmc_raw_read()