Lines Matching +full:0 +full:x01ffffff
40 #define PCAP_REGISTER_WRITE_OP_BIT 0x80000000
41 #define PCAP_REGISTER_READ_OP_BIT 0x00000000
43 #define PCAP_REGISTER_VALUE_MASK 0x01ffffff
44 #define PCAP_REGISTER_ADDRESS_MASK 0x7c000000
47 #define PCAP_CLEAR_INTERRUPT_REGISTER 0x01ffffff
48 #define PCAP_MASK_ALL_INTERRUPT 0x01ffffff
51 #define PCAP_REG_ISR 0x0 /* Interrupt Status */
52 #define PCAP_REG_MSR 0x1 /* Interrupt Mask */
53 #define PCAP_REG_PSTAT 0x2 /* Processor Status */
54 #define PCAP_REG_VREG2 0x6 /* Regulator Bank 2 Control */
55 #define PCAP_REG_AUXVREG 0x7 /* Auxiliary Regulator Control */
56 #define PCAP_REG_BATT 0x8 /* Battery Control */
57 #define PCAP_REG_ADC 0x9 /* AD Control */
58 #define PCAP_REG_ADR 0xa /* AD Result */
59 #define PCAP_REG_CODEC 0xb /* Audio Codec Control */
60 #define PCAP_REG_RX_AMPS 0xc /* RX Audio Amplifiers Control */
61 #define PCAP_REG_ST_DAC 0xd /* Stereo DAC Control */
62 #define PCAP_REG_BUSCTRL 0x14 /* Connectivity Control */
63 #define PCAP_REG_PERIPH 0x15 /* Peripheral Control */
64 #define PCAP_REG_LOWPWR 0x18 /* Regulator Low Power Control */
65 #define PCAP_REG_TX_AMPS 0x1a /* TX Audio Amplifiers Control */
66 #define PCAP_REG_GP 0x1b /* General Purpose */
67 #define PCAP_REG_TEST1 0x1c
68 #define PCAP_REG_TEST2 0x1d
69 #define PCAP_REG_VENDOR_TEST1 0x1e
70 #define PCAP_REG_VENDOR_TEST2 0x1f
73 #define PCAP_REG_INT_SEL 0x3 /* Interrupt Select */
74 #define PCAP_REG_SWCTRL 0x4 /* Switching Regulator Control */
75 #define PCAP_REG_VREG1 0x5 /* Regulator Bank 1 Control */
76 #define PCAP_REG_RTC_TOD 0xe /* RTC Time of Day */
77 #define PCAP_REG_RTC_TODA 0xf /* RTC Time of Day Alarm */
78 #define PCAP_REG_RTC_DAY 0x10 /* RTC Day */
79 #define PCAP_REG_RTC_DAYA 0x11 /* RTC Day Alarm */
80 #define PCAP_REG_MTRTMR 0x12 /* AD Monitor Timer */
81 #define PCAP_REG_PWR 0x13 /* Power Control */
82 #define PCAP_REG_AUXVREG_MASK 0x16 /* Auxiliary Regulator Mask */
83 #define PCAP_REG_VENDOR_REV 0x17
84 #define PCAP_REG_PERIPH_MASK 0x19 /* Peripheral Mask */
88 #define PCAP_IRQ_ADCDONE 0 /* ADC done port 1 */
113 #define V1 0
136 #define PCAP_BATT_DAC_MASK 0x000000ff
137 #define PCAP_BATT_DAC_SHIFT 0
140 #define PCAP_BATT_V_COIN_MASK 0x00003c00
144 #define PCAP_BATT_EOL_SEL_MASK 0x000e0000
150 #define PCAP_ADC_ADEN (1 << 0)
154 #define PCAP_ADC_ADA1_MASK 0x00000070
156 #define PCAP_ADC_ADA2_MASK 0x00000380
158 #define PCAP_ADC_ATO_MASK 0x00003c00
163 #define PCAP_ADC_TS_M_MASK 0x000e0000
170 #define PCAP_ADC_BANK_0 0
172 /* ADC bank 0 */
173 #define PCAP_ADC_CH_COIN 0
181 #define PCAP_ADC_CH_AD7 0
189 #define PCAP_ADC_T_NOW 0
194 #define PCAP_ADC_ATO_OUT_BURST 0
203 #define PCAP_ADR_ADD1_MASK 0x000003ff
204 #define PCAP_ADR_ADD1_SHIFT 0
205 #define PCAP_ADR_ADD2_MASK 0x000ffc00
212 #define PCAP_BUSCTRL_FSENB (1 << 0)
228 #define PCAP_LED0 0
232 #define PCAP_LED_3MA 0
236 #define PCAP_LED_T_MASK 0xf
237 #define PCAP_LED_C_MASK 0x3
238 #define PCAP_BL_MASK 0x1f
239 #define PCAP_BL0_SHIFT 0
249 #define PCAP_RTC_DAY_MASK 0x3fff
250 #define PCAP_RTC_TOD_MASK 0xffff
251 #define PCAP_RTC_PC_MASK 0x7