linux/mfd/dbx500-prcmu.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
5  * STE Ux500 PRCMU API
14 #include <dt-bindings/mfd/dbx500-prcmu.h> /* For clock identifiers */
20 /* PRCMU Wakeup defines */
40  * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
41  * - EPOD_ID_SVAPIPE: power domain for SVA pipe
42  * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
43  * - EPOD_ID_SIAPIPE: power domain for SIA pipe
44  * - EPOD_ID_SGA: power domain for SGA
45  * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
46  * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
47  * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
48  * - NUM_EPOD_ID: number of power domains
56 #define EPOD_ID_SGA		4
64  * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
65  * - EPOD_STATE_OFF: The EPOD is switched off
66  * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
68  * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
69  * - EPOD_STATE_ON: Same as above, but with clock enabled
99  * enum prcmu_wdog_id - PRCMU watchdog IDs
101  * @PRCMU_WDOG_CPU1: use first CPU timer only
102  * @PRCMU_WDOG_CPU2: use second CPU timer conly
111  * enum ape_opp - APE OPP states definition
127  * enum arm_opp - ARM OPP states definition
147  * enum ddr_opp - DDR OPP states definition
165  * enum ddr_pwrst - DDR power states definition
182 #define PRCMU_FW_PROJECT_U9500		4 /* Customer specific */
212 #include <linux/mfd/db8500-prcmu.h>
410 	return -ENOSYS;  in prcmu_abb_read()
415 	return -ENOSYS;  in prcmu_abb_write()
421 	return -ENOSYS;  in prcmu_abb_write_masked()
553 /* PRCMU QoS APE OPP class */
557 #define PRCMU_QOS_DEFAULT_VALUE -1