linux/irqchip/irq-bcm2836.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
12  * The low 2 bits identify the CPU that the GPU IRQ goes to, and the
13  * next 2 bits identify the CPU that the GPU FIQ goes to.
16 /* When setting bits 0-3, enables PMU interrupts on that CPU. */
18 /* When setting bits 0-3, disables PMU interrupts on that CPU. */
21  * The low 4 bits of this are the CPU's timer IRQ enables, and the
22  * next 4 bits are the CPU's timer FIQ enables (which override the IRQ
23  * bits).
27  * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and
28  * the next 4 bits are the CPU's per-mailbox FIQ enables (which
29  * override the IRQ bits).
33  * The CPU's interrupt status register.  Bits are defined by the
34  * LOCAL_IRQ_* bits below.
37 /* Same status bits as above, but for FIQ. */
40  * Mailbox write-to-set bits.  There are 16 mailboxes, 4 per CPU, and
41  * these bits are organized by mailbox number and then CPU number.  We
47 /* Mailbox write-to-clear bits. */
55 #define LOCAL_IRQ_MAILBOX0	4