linux/clk/ti.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
3  * TI clock drivers support
10 #include <linux/clk-provider.h>
14  * struct clk_omap_reg - OMAP register declaration
15  * @offset: offset from the master IP module base address
17  * @index: index of the master IP module
29  * struct dpll_data - DPLL registers and integration data
33  * @clk_bypass: struct clk_hw pointer to the clock's bypass clock input
34  * @clk_ref: struct clk_hw pointer to the clock's reference clock input
43  * @max_multiplier: maximum valid non-bypass multiplier value (actual)
45  * @min_divider: minimum valid non-bypass divider value (actual)
46  * @max_divider: maximum valid non-bypass divider value (actual)
47  * @max_rate: maximum clock rate for the DPLL
56  * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
61  * @ssc_deltam_reg: register containing the DPLL SSC frequency spreading
62  * @ssc_modfreq_reg: register containing the DPLL SSC modulation frequency
66  * @ssc_downspread_mask: mask of the DPLL SSC low frequency only bit in
68  * @ssc_modfreq: the DPLL SSC frequency modulation in kHz
69  * @ssc_deltam: the DPLL SSC frequency spreading in permille (10th of percent)
70  * @ssc_downspread: require the only low frequency spread of the DPLL in SSC
75  * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
82  * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
83  * @last_rounded_n) should be separated from the runtime-fixed fields
84  * and placed into a different structure, so that the runtime-fixed data
85  * can be placed into read-only space.
136  * struct clk_hw_omap_ops - OMAP clk ops
137  * @find_idlest: find idlest register information for a clock
138  * @find_companion: find companion clock register information for a clock,
139  *		    basically converts CM_ICLKEN* <-> CM_FCLKEN*
140  * @allow_idle: enables autoidle hardware functionality for a clock
141  * @deny_idle: prevent autoidle hardware functionality for a clock
155  * struct clk_hw_omap - OMAP struct clk
156  * @node: list_head connecting this clock into the full clock list
157  * @enable_reg: register to write to enable the clock (see @enable_bit)
158  * @enable_bit: bitshift to write to enable/disable the clock (see @enable_reg)
161  * @dpll_data: for DPLLs, pointer to struct dpll_data for this clock
162  * @clkdm_name: clockdomain name that this clock is contained in
164  * @ops: clock ops for this clock
186  * XXX document the rest of the clock flags here
188  * ENABLE_REG_32BIT: (OMAP1 only) clock control register must be accessed
190  * CLOCK_IDLE_CONTROL: (OMAP1 only) clock has autoidle support.
191  * CLOCK_NO_IDLE_PARENT: (OMAP1 only) when clock is enabled, its parent
192  *     clock is put to no-idle mode.
193  * ENABLE_ON_INIT: Clock is enabled on init.
194  * INVERT_ENABLE: By default, clock enable bit behavior is '1' enable, '0'
199  *     should be used.  This is a temporary solution - a better approach
200  *     would be to associate clock type-specific data with the clock,
203 #define ENABLE_REG_32BIT	(1 << 0)	/* Use 32-bit access */
210 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
231  * struct ti_clk_ll_ops - low-level ops for clocks
234  * @clk_rmw: pointer to register read-modify-write function
241  * Low-level ops are generally used by the basic clock types (clk-gate,
242  * clk-mux, clk-divider etc.) to provide support for various low-level
244  * by board code. Low-level ops also contain some other platform specific
245  * operations not provided directly by clock drivers.
333 static inline int omap3430_clk_legacy_init(void) { return -ENXIO; }  in omap3430_clk_legacy_init()
334 static inline int omap3430es1_clk_legacy_init(void) { return -ENXIO; }  in omap3430es1_clk_legacy_init()
335 static inline int omap36xx_clk_legacy_init(void) { return -ENXIO; }  in omap36xx_clk_legacy_init()
336 static inline int am35xx_clk_legacy_init(void) { return -ENXIO; }  in am35xx_clk_legacy_init()