linux/clk/ti.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
10 #include <linux/clk-provider.h>
14  * struct clk_omap_reg - OMAP register declaration
29  * struct dpll_data - DPLL registers and integration data
31  * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
32  * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
36  * @enable_mask: mask of the DPLL mode bitfield in @control_reg
43  * @max_multiplier: maximum valid non-bypass multiplier value (actual)
45  * @min_divider: minimum valid non-bypass divider value (actual)
46  * @max_divider: maximum valid non-bypass divider value (actual)
51  * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
52  * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
53  * @dcc_mask: mask of the DPLL DCC correction bitfield @mult_div1_reg
55  * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
56  * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
57  * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
63  * @ssc_modfreq_mant_mask: mask of the mantissa component in @ssc_modfreq_reg
64  * @ssc_modfreq_exp_mask: mask of the exponent component in @ssc_modfreq_reg
65  * @ssc_enable_mask: mask of the DPLL SSC enable bit in @control_reg
66  * @ssc_downspread_mask: mask of the DPLL SSC low frequency only bit in
75  * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
82  * XXX The runtime-variable fields (@last_rounded_rate, @last_rounded_m,
83  * @last_rounded_n) should be separated from the runtime-fixed fields
84  * and placed into a different structure, so that the runtime-fixed data
85  * can be placed into read-only space.
136  * struct clk_hw_omap_ops - OMAP clk ops
139  *		    basically converts CM_ICLKEN* <-> CM_FCLKEN*
155  * struct clk_hw_omap - OMAP struct clk
192  *     clock is put to no-idle mode.
199  *     should be used.  This is a temporary solution - a better approach
200  *     would be to associate clock type-specific data with the clock,
203 #define ENABLE_REG_32BIT	(1 << 0)	/* Use 32-bit access */
210 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
231  * struct ti_clk_ll_ops - low-level ops for clocks
232  * @clk_readl: pointer to register read function
233  * @clk_writel: pointer to register write function
234  * @clk_rmw: pointer to register read-modify-write function
235  * @clkdm_clk_enable: pointer to clockdomain enable function
236  * @clkdm_clk_disable: pointer to clockdomain disable function
237  * @clkdm_lookup: pointer to clockdomain lookup function
238  * @cm_wait_module_ready: pointer to CM module wait ready function
239  * @cm_split_idlest_reg: pointer to CM module function to split idlest reg
241  * Low-level ops are generally used by the basic clock types (clk-gate,
242  * clk-mux, clk-divider etc.) to provide support for various low-level
244  * by board code. Low-level ops also contain some other platform specific
250 	void	(*clk_rmw)(u32 val, u32 mask, const struct clk_omap_reg *reg);
333 static inline int omap3430_clk_legacy_init(void) { return -ENXIO; }  in omap3430_clk_legacy_init()
334 static inline int omap3430es1_clk_legacy_init(void) { return -ENXIO; }  in omap3430es1_clk_legacy_init()
335 static inline int omap36xx_clk_legacy_init(void) { return -ENXIO; }  in omap36xx_clk_legacy_init()
336 static inline int am35xx_clk_legacy_init(void) { return -ENXIO; }  in am35xx_clk_legacy_init()