linux/clk/ti.h

29  * struct dpll_data - DPLL registers and integration data
30  * @mult_div1_reg: register containing the DPLL M and N bitfields
31  * @mult_mask: mask of the DPLL M bitfield in @mult_div1_reg
32  * @div1_mask: mask of the DPLL N bitfield in @mult_div1_reg
35  * @control_reg: register containing the DPLL mode bitfield
36  * @enable_mask: mask of the DPLL mode bitfield in @control_reg
47  * @max_rate: maximum clock rate for the DPLL
49  * @autoidle_reg: register containing the DPLL autoidle mode bitfield
50  * @idlest_reg: register containing the DPLL idle status bitfield
51  * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
52  * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
53  * @dcc_mask: mask of the DPLL DCC correction bitfield @mult_div1_reg
55  * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
56  * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
57  * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
61  * @ssc_deltam_reg: register containing the DPLL SSC frequency spreading
62  * @ssc_modfreq_reg: register containing the DPLL SSC modulation frequency
65  * @ssc_enable_mask: mask of the DPLL SSC enable bit in @control_reg
66  * @ssc_downspread_mask: mask of the DPLL SSC low frequency only bit in
68  * @ssc_modfreq: the DPLL SSC frequency modulation in kHz
69  * @ssc_deltam: the DPLL SSC frequency spreading in permille (10th of percent)
70  * @ssc_downspread: require the only low frequency spread of the DPLL in SSC
72  * @flags: DPLL type/features (see below)
75  * DPLL_J_TYPE: "J-type DPLL" (only some 36xx, 4xxx DPLLs)
196  * CLOCK_CLKOUTX2: (OMAP4 only) DPLL CLKOUT and CLKOUTX2 GATE_CTRL
210 /* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
215 /* DPLL Type and DCO Selection Flags */