include/linux/clk-provider.h

1 /* SPDX-License-Identifier: GPL-2.0 */
3  *  Copyright (c) 2010-2011 Jeremy Kerr <jeremy.kerr@canonical.com>
4  *  Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
14  * top-level framework.  custom flags for dealing with hardware specifics
20 #define CLK_SET_PARENT_GATE	BIT(1) /* must be gated across re-parent */
26 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
31 /* parents need enable during gate/ungate, set rate and re-parent */
42  * struct clk_rate_request - Structure encoding the clk constraints that
77  * struct clk_duty - Structure encoding the duty cycle ratio of a clock
88  * struct clk_ops -  Callback operations for hardware clocks; these are to
136  *		0. Returns the calculated rate. Optional, but recommended - if
152  *		Returns 0 on success, -EERROR otherwise.
168  *		Returns 0 on success, -EERROR otherwise.
179  *		Returns 0 on success, -EERROR otherwise.
184  *		Returns the calculated accuracy.  Optional - if	this op is not
189  *		Returned values are 0-359 degrees on success, negative
194  *		0-359. Return 0 on success, otherwise -EERROR.
203  *              and >= numerator) Return 0 on success, otherwise -EERROR.
205  * @init:	Perform platform-specific initialization magic.
212  *		Returns 0 on success, -EERROR otherwise.
216  * @debug_init:	Set up type-specific debugfs entries for this clock.  This
220  *		prepare_lock held.  Returns 0 on success, -EERROR otherwise.
230  * (eg. when a device is opened), and clk_enable when the clock is actually
272  * struct clk_parent_data - clk parent information
286  * struct clk_init_data - holds init data that's common to all clocks and is
297  * @flags: framework-level hints and quirks
311  * struct clk_hw - handle for traversing from a struct clk to its corresponding
312  * hardware-specific structure.  struct clk_hw should be declared within struct
319  * @clk: pointer to the per-user struct clk instance that can be used to call
342  * struct clk_fixed_rate - fixed-rate clock
343  * @hw:		handle between common and hardware-specific interfaces
346  * @flags:	hardware specific flags
349  * * CLK_FIXED_RATE_PARENT_ACCURACY - Use the accuracy of the parent clk
362 struct clk_hw *__clk_hw_register_fixed_rate(struct device *dev,
368 struct clk *clk_register_fixed_rate(struct device *dev, const char *name,
372  * clk_hw_register_fixed_rate - register fixed-rate clock with the clock
374  * @dev: device that is registering this clock
377  * @flags: framework-specific flags
378  * @fixed_rate: non-adjustable clock rate
385  * devm_clk_hw_register_fixed_rate - register fixed-rate clock with the clock
387  * @dev: device that is registering this clock
390  * @flags: framework-specific flags
391  * @fixed_rate: non-adjustable clock rate
397  * devm_clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
399  * @dev: device that is registering this clock
402  * @flags: framework-specific flags
403  * @fixed_rate: non-adjustable clock rate
411  * clk_hw_register_fixed_rate_parent_hw - register fixed-rate clock with
413  * @dev: device that is registering this clock
416  * @flags: framework-specific flags
417  * @fixed_rate: non-adjustable clock rate
424  * clk_hw_register_fixed_rate_parent_data - register fixed-rate clock with
426  * @dev: device that is registering this clock
429  * @flags: framework-specific flags
430  * @fixed_rate: non-adjustable clock rate
438  * clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
440  * @dev: device that is registering this clock
443  * @flags: framework-specific flags
444  * @fixed_rate: non-adjustable clock rate
445  * @fixed_accuracy: non-adjustable clock accuracy
454  * clk_hw_register_fixed_rate_with_accuracy_parent_hw - register fixed-rate
456  * @dev: device that is registering this clock
459  * @flags: framework-specific flags
460  * @fixed_rate: non-adjustable clock rate
461  * @fixed_accuracy: non-adjustable clock accuracy
469  * clk_hw_register_fixed_rate_with_accuracy_parent_data - register fixed-rate
471  * @dev: device that is registering this clock
474  * @flags: framework-specific flags
475  * @fixed_rate: non-adjustable clock rate
476  * @fixed_accuracy: non-adjustable clock accuracy
484  * clk_hw_register_fixed_rate_parent_accuracy - register fixed-rate clock with
486  * @dev: device that is registering this clock
489  * @flags: framework-specific flags
490  * @fixed_rate: non-adjustable clock rate
504  * struct clk_gate - gating clock
506  * @hw:		handle between common and hardware-specific interfaces
509  * @flags:	hardware-specific flags
515  * CLK_GATE_SET_TO_DISABLE - by default this clock sets the bit at bit_idx to
518  * CLK_GATE_HIWORD_MASK - The gate settings are only in lower 16-bit
519  *	of this register, and mask of gate bits are in higher 16-bit of this
520  *	register.  While setting the gate bits, higher 16-bit should also be
522  * CLK_GATE_BIG_ENDIAN - by default little endian register accesses are used for
541 struct clk_hw *__clk_hw_register_gate(struct device *dev,
548 struct clk_hw *__devm_clk_hw_register_gate(struct device *dev,
555 struct clk *clk_register_gate(struct device *dev, const char *name,
560  * clk_hw_register_gate - register a gate clock with the clock framework
561  * @dev: device that is registering this clock
564  * @flags: framework-specific flags for this clock
567  * @clk_gate_flags: gate-specific flags for this clock
576  * clk_hw_register_gate_parent_hw - register a gate clock with the clock
578  * @dev: device that is registering this clock
581  * @flags: framework-specific flags for this clock
584  * @clk_gate_flags: gate-specific flags for this clock
593  * clk_hw_register_gate_parent_data - register a gate clock with the clock
595  * @dev: device that is registering this clock
598  * @flags: framework-specific flags for this clock
601  * @clk_gate_flags: gate-specific flags for this clock
610  * devm_clk_hw_register_gate - register a gate clock with the clock framework
611  * @dev: device that is registering this clock
614  * @flags: framework-specific flags for this clock
617  * @clk_gate_flags: gate-specific flags for this clock
626  * devm_clk_hw_register_gate_parent_data - register a gate clock with the
628  * @dev: device that is registering this clock
631  * @flags: framework-specific flags for this clock
634  * @clk_gate_flags: gate-specific flags for this clock
654  * struct clk_divider - adjustable divider clock
656  * @hw:		handle between common and hardware-specific interfaces
667  * CLK_DIVIDER_ONE_BASED - by default the divisor is the value read from the
671  * CLK_DIVIDER_POWER_OF_TWO - clock divisor is 2 raised to the value read from
673  * CLK_DIVIDER_ALLOW_ZERO - Allow zero divisors.  For dividers which have
678  * CLK_DIVIDER_HIWORD_MASK - The divider settings are only in lower 16-bit
679  *	of this register, and mask of divider bits are in higher 16-bit of this
680  *	register.  While setting the divider bits, higher 16-bit should also be
682  * CLK_DIVIDER_ROUND_CLOSEST - Makes the best calculated divider to be rounded
684  * CLK_DIVIDER_READ_ONLY - The divider settings are preconfigured and should
686  * CLK_DIVIDER_MAX_AT_ZERO - For dividers which are like CLK_DIVIDER_ONE_BASED
689  * CLK_DIVIDER_BIG_ENDIAN - By default little endian register accesses are used
703 #define clk_div_mask(width)	((1 << (width)) - 1)
739 struct clk_hw *__clk_hw_register_divider(struct device *dev,
745 struct clk_hw *__devm_clk_hw_register_divider(struct device *dev,
751 struct clk *clk_register_divider_table(struct device *dev, const char *name,
757  * clk_register_divider - register a divider clock with the clock framework
758  * @dev: device registering this clock
761  * @flags: framework-specific flags
765  * @clk_divider_flags: divider-specific flags for this clock
774  * clk_hw_register_divider - register a divider clock with the clock framework
775  * @dev: device registering this clock
778  * @flags: framework-specific flags
782  * @clk_divider_flags: divider-specific flags for this clock
791  * clk_hw_register_divider_parent_hw - register a divider clock with the clock
793  * @dev: device registering this clock
796  * @flags: framework-specific flags
800  * @clk_divider_flags: divider-specific flags for this clock
810  * clk_hw_register_divider_parent_data - register a divider clock with the clock
812  * @dev: device registering this clock
815  * @flags: framework-specific flags
819  * @clk_divider_flags: divider-specific flags for this clock
829  * clk_hw_register_divider_table - register a table based divider clock with
831  * @dev: device registering this clock
834  * @flags: framework-specific flags
838  * @clk_divider_flags: divider-specific flags for this clock
849  * clk_hw_register_divider_table_parent_hw - register a table based divider
851  * @dev: device registering this clock
854  * @flags: framework-specific flags
858  * @clk_divider_flags: divider-specific flags for this clock
870  * clk_hw_register_divider_table_parent_data - register a table based divider
872  * @dev: device registering this clock
875  * @flags: framework-specific flags
879  * @clk_divider_flags: divider-specific flags for this clock
892  * devm_clk_hw_register_divider - register a divider clock with the clock framework
893  * @dev: device registering this clock
896  * @flags: framework-specific flags
900  * @clk_divider_flags: divider-specific flags for this clock
909  * devm_clk_hw_register_divider_parent_hw - register a divider clock with the clock framework
910  * @dev: device registering this clock
913  * @flags: framework-specific flags
917  * @clk_divider_flags: divider-specific flags for this clock
928  * devm_clk_hw_register_divider_table - register a table based divider clock
930  * @dev: device registering this clock
933  * @flags: framework-specific flags
937  * @clk_divider_flags: divider-specific flags for this clock
953  * struct clk_mux - multiplexer clock
955  * @hw:		handle between common and hardware-specific interfaces
960  * @flags:	hardware-specific flags
967  * CLK_MUX_INDEX_ONE - register index starts at 1, not 0
968  * CLK_MUX_INDEX_BIT - register index is a single bit (power of two)
969  * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
970  *	register, and mask of mux bits are in higher 16-bit of this register.
971  *	While setting the mux bits, higher 16-bit should also be updated to
973  * CLK_MUX_READ_ONLY - The mux registers can't be written, only read in the
975  * CLK_MUX_ROUND_CLOSEST - Use the parent rate that is closest to the desired
977  * CLK_MUX_BIG_ENDIAN - By default little endian register accesses are used for
1003 struct clk_hw *__clk_hw_register_mux(struct device *dev, struct device_node *np,
1010 struct clk_hw *__devm_clk_hw_register_mux(struct device *dev, struct device_node *np,
1017 struct clk *clk_register_mux_table(struct device *dev, const char *name,
1025 			       (flags), (reg), (shift), BIT((width)) - 1,     \
1045 			      (shift), BIT((width)) - 1, (clk_mux_flags),     \
1051 			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1057 			      BIT((width)) - 1, (clk_mux_flags), NULL, (lock))
1064 			      BIT((width)) - 1, (clk_mux_flags), table, (lock))
1069 			      (shift), BIT((width)) - 1, (clk_mux_flags),     \
1076 				   (shift), BIT((width)) - 1,		      \
1084 			      BIT((width)) - 1, (clk_mux_flags), table, (lock))
1096  * struct clk_fixed_factor - fixed multiplier and divider clock
1098  * @hw:		handle between common and hardware-specific interfaces
1109  * * CLK_FIXED_FACTOR_FIXED_ACCURACY - Use the value in @acc instead of the
1126 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
1130 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
1133 struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev,
1136 struct clk_hw *clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev,
1141 struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
1144 struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev,
1147 struct clk_hw *devm_clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev,
1151 struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev,
1155 struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev,
1159 struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev,
1163  * struct clk_fractional_divider - adjustable fractional divider clock
1165  * @hw:		handle between common and hardware-specific interfaces
1177  * CLK_FRAC_DIVIDER_ZERO_BASED - by default the numerator and denominator
1181  * CLK_FRAC_DIVIDER_BIG_ENDIAN - By default little endian register accesses are
1184  * CLK_FRAC_DIVIDER_POWER_OF_TWO_PS - By default the resulting fraction might
1189  *	caller's side the power-of-two capable prescaler exists.
1211 struct clk *clk_register_fractional_divider(struct device *dev,
1215 struct clk_hw *clk_hw_register_fractional_divider(struct device *dev,
1222  * struct clk_multiplier - adjustable multiplier clock
1224  * @hw:		handle between common and hardware-specific interfaces
1234  * CLK_MULTIPLIER_ZERO_BYPASS - By default, the multiplier is the value read
1239  * CLK_MULTIPLIER_ROUND_CLOSEST - Makes the best calculated divider to be
1241  * CLK_MULTIPLIER_BIG_ENDIAN - By default little endian register accesses are
1263  * struct clk_composite - aggregate clock of mux, divider and gate clocks
1265  * @hw:		handle between common and hardware-specific interfaces
1266  * @mux_hw:	handle between composite and hardware-specific mux clock
1267  * @rate_hw:	handle between composite and hardware-specific rate clock
1268  * @gate_hw:	handle between composite and hardware-specific gate clock
1288 struct clk *clk_register_composite(struct device *dev, const char *name,
1294 struct clk *clk_register_composite_pdata(struct device *dev, const char *name,
1301 struct clk_hw *clk_hw_register_composite(struct device *dev, const char *name,
1307 struct clk_hw *clk_hw_register_composite_pdata(struct device *dev,
1314 struct clk_hw *devm_clk_hw_register_composite_pdata(struct device *dev,
1323 struct clk *clk_register(struct device *dev, struct clk_hw *hw);
1324 struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
1326 int __must_check clk_hw_register(struct device *dev, struct clk_hw *hw);
1327 int __must_check devm_clk_hw_register(struct device *dev, struct clk_hw *hw);
1347 struct clk *devm_clk_hw_get_clk(struct device *dev, struct clk_hw *hw,
1385 	dst->clk = src->clk;  in __clk_hw_set_clk()
1386 	dst->core = src->core;  in __clk_hw_set_clk()
1434  * routines, one at of_clk_init(), and one at platform device probe
1580 int devm_of_clk_add_hw_provider(struct device *dev,
1614 static inline int devm_of_clk_add_hw_provider(struct device *dev,  in devm_of_clk_add_hw_provider()
1626 	return ERR_PTR(-ENOENT);  in of_clk_src_simple_get()
1631 	return ERR_PTR(-ENOENT);  in of_clk_hw_simple_get()
1636 	return ERR_PTR(-ENOENT);  in of_clk_src_onecell_get()
1641 	return ERR_PTR(-ENOENT);  in of_clk_hw_onecell_get()