linux/amba/serial.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3  *  linux/include/asm-arm/hardware/serial_amba.h
20 /* -------------------------------------------------------------------------------
22  * -------------------------------------------------------------------------------
27 #define UART01x_ECR		0x04	/* Error clear register (Write). */
36 #define UART010_ICR		0x1C	/* Interrupt clear register (Write). */
48 #define UART011_ICR		0x44	/* Interrupt clear register. */
58 #define ST_UART011_ABIMSC	0x15C	/* Autobaud interrupt mask/clear register. */
78 #define UART011_DR_OE		BIT(11)
79 #define UART011_DR_BE		BIT(10)
80 #define UART011_DR_PE		BIT(9)
81 #define UART011_DR_FE		BIT(8)
83 #define UART01x_RSR_OE		BIT(3)
84 #define UART01x_RSR_BE		BIT(2)
85 #define UART01x_RSR_PE		BIT(1)
86 #define UART01x_RSR_FE		BIT(0)
88 #define UART011_FR_RI		BIT(8)
89 #define UART011_FR_TXFE		BIT(7)
90 #define UART011_FR_RXFF		BIT(6)
92 #define UART01x_FR_RXFE		BIT(4)
94 #define UART01x_FR_DCD		BIT(2)
95 #define UART01x_FR_DSR		BIT(1)
96 #define UART01x_FR_CTS		BIT(0)
103 #define ZX_UART01x_FR_BUSY	BIT(8)
104 #define ZX_UART01x_FR_DSR	BIT(3)
105 #define ZX_UART01x_FR_CTS	BIT(1)
106 #define ZX_UART011_FR_RI	BIT(0)
108 #define UART011_CR_CTSEN	BIT(15)	/* CTS hardware flow control */
109 #define UART011_CR_RTSEN	BIT(14)	/* RTS hardware flow control */
110 #define UART011_CR_OUT2		BIT(13)	/* OUT2 */
111 #define UART011_CR_OUT1		BIT(12)	/* OUT1 */
112 #define UART011_CR_RTS		BIT(11)	/* RTS */
113 #define UART011_CR_DTR		BIT(10)	/* DTR */
114 #define UART011_CR_RXE		BIT(9)	/* receive enable */
115 #define UART011_CR_TXE		BIT(8)	/* transmit enable */
116 #define UART011_CR_LBE		BIT(7)	/* loopback enable */
117 #define UART010_CR_RTIE		BIT(6)
118 #define UART010_CR_TIE		BIT(5)
119 #define UART010_CR_RIE		BIT(4)
120 #define UART010_CR_MSIE		BIT(3)
121 #define ST_UART011_CR_OVSFACT	BIT(3)	/* Oversampling factor */
122 #define UART01x_CR_IIRLP	BIT(2)	/* SIR low power mode */
123 #define UART01x_CR_SIREN	BIT(1)	/* SIR enable */
124 #define UART01x_CR_UARTEN	BIT(0)	/* UART enable */
126 #define UART011_LCRH_SPS	BIT(7)
131 #define UART01x_LCRH_FEN	BIT(4)
132 #define UART01x_LCRH_STP2	BIT(3)
133 #define UART01x_LCRH_EPS	BIT(2)
134 #define UART01x_LCRH_PEN	BIT(1)
135 #define UART01x_LCRH_BRK	BIT(0)
154 #define UART010_IIR_RTIS	BIT(3)
155 #define UART010_IIR_TIS		BIT(2)
156 #define UART010_IIR_RIS		BIT(1)
157 #define UART010_IIR_MIS		BIT(0)
175 #define UART011_OEIM		BIT(10)	/* overrun error interrupt mask */
176 #define UART011_BEIM		BIT(9)	/* break error interrupt mask */
177 #define UART011_PEIM		BIT(8)	/* parity error interrupt mask */
178 #define UART011_FEIM		BIT(7)	/* framing error interrupt mask */
179 #define UART011_RTIM		BIT(6)	/* receive timeout interrupt mask */
180 #define UART011_TXIM		BIT(5)	/* transmit interrupt mask */
181 #define UART011_RXIM		BIT(4)	/* receive interrupt mask */
182 #define UART011_DSRMIM		BIT(3)	/* DSR interrupt mask */
183 #define UART011_DCDMIM		BIT(2)	/* DCD interrupt mask */
184 #define UART011_CTSMIM		BIT(1)	/* CTS interrupt mask */
185 #define UART011_RIMIM		BIT(0)	/* RI interrupt mask */
187 #define UART011_OEIS		BIT(10)	/* overrun error interrupt status */
188 #define UART011_BEIS		BIT(9)	/* break error interrupt status */
189 #define UART011_PEIS		BIT(8)	/* parity error interrupt status */
190 #define UART011_FEIS		BIT(7)	/* framing error interrupt status */
191 #define UART011_RTIS		BIT(6)	/* receive timeout interrupt status */
192 #define UART011_TXIS		BIT(5)	/* transmit interrupt status */
193 #define UART011_RXIS		BIT(4)	/* receive interrupt status */
194 #define UART011_DSRMIS		BIT(3)	/* DSR interrupt status */
195 #define UART011_DCDMIS		BIT(2)	/* DCD interrupt status */
196 #define UART011_CTSMIS		BIT(1)	/* CTS interrupt status */
197 #define UART011_RIMIS		BIT(0)	/* RI interrupt status */
199 #define UART011_OEIC		BIT(10)	/* overrun error interrupt clear */
200 #define UART011_BEIC		BIT(9)	/* break error interrupt clear */
201 #define UART011_PEIC		BIT(8)	/* parity error interrupt clear */
202 #define UART011_FEIC		BIT(7)	/* framing error interrupt clear */
203 #define UART011_RTIC		BIT(6)	/* receive timeout interrupt clear */
204 #define UART011_TXIC		BIT(5)	/* transmit interrupt clear */
205 #define UART011_RXIC		BIT(4)	/* receive interrupt clear */
206 #define UART011_DSRMIC		BIT(3)	/* DSR interrupt clear */
207 #define UART011_DCDMIC		BIT(2)	/* DCD interrupt clear */
208 #define UART011_CTSMIC		BIT(1)	/* CTS interrupt clear */
209 #define UART011_RIMIC		BIT(0)	/* RI interrupt clear */
211 #define UART011_DMAONERR	BIT(2)	/* disable dma on error */
212 #define UART011_TXDMAE		BIT(1)	/* enable transmit dma */
213 #define UART011_RXDMAE		BIT(0)	/* enable receive dma */