Lines Matching full:clear

27 #define UART01x_ECR		0x04	/* Error clear register (Write). */
36 #define UART010_ICR		0x1C	/* Interrupt clear register (Write). */
48 #define UART011_ICR		0x44	/* Interrupt clear register. */
58 #define ST_UART011_ABIMSC	0x15C	/* Autobaud interrupt mask/clear register. */
199 #define UART011_OEIC		BIT(10)	/* overrun error interrupt clear */
200 #define UART011_BEIC		BIT(9)	/* break error interrupt clear */
201 #define UART011_PEIC		BIT(8)	/* parity error interrupt clear */
202 #define UART011_FEIC		BIT(7)	/* framing error interrupt clear */
203 #define UART011_RTIC		BIT(6)	/* receive timeout interrupt clear */
204 #define UART011_TXIC		BIT(5)	/* transmit interrupt clear */
205 #define UART011_RXIC		BIT(4)	/* receive interrupt clear */
206 #define UART011_DSRMIC		BIT(3)	/* DSR interrupt clear */
207 #define UART011_DCDMIC		BIT(2)	/* DCD interrupt clear */
208 #define UART011_CTSMIC		BIT(1)	/* CTS interrupt clear */
209 #define UART011_RIMIC		BIT(0)	/* RI interrupt clear */