dt-bindings/memory/mt8195-memory-port.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <dt-bindings/memory/mtk-memory-port.h>
13  * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
16  * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
20  * modules    dma-address-region	larbs-ports
22  * vcodec      4G ~ 8G                  larb19/20/21/22/23/24
23  * cam/mdp     8G ~ 12G                 the other larbs.
29  * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
30  * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27
95 #define M4U_PORT_L8_IMG_WPE_RDMA0		MTK_M4U_ID(8, 0)
96 #define M4U_PORT_L8_IMG_WPE_RDMA1		MTK_M4U_ID(8, 1)
97 #define M4U_PORT_L8_IMG_WPE_WDMA0		MTK_M4U_ID(8, 2)
100 #define M4U_PORT_L9_IMG_IMGI_T1_A		MTK_M4U_ID(9, 0)
101 #define M4U_PORT_L9_IMG_IMGBI_T1_A		MTK_M4U_ID(9, 1)
102 #define M4U_PORT_L9_IMG_IMGCI_T1_A		MTK_M4U_ID(9, 2)
103 #define M4U_PORT_L9_IMG_SMTI_T1_A		MTK_M4U_ID(9, 3)
104 #define M4U_PORT_L9_IMG_TNCSTI_T1_A		MTK_M4U_ID(9, 4)
105 #define M4U_PORT_L9_IMG_TNCSTI_T4_A		MTK_M4U_ID(9, 5)
106 #define M4U_PORT_L9_IMG_YUVO_T1_A		MTK_M4U_ID(9, 6)
107 #define M4U_PORT_L9_IMG_TIMGO_T1_A		MTK_M4U_ID(9, 7)
108 #define M4U_PORT_L9_IMG_YUVO_T2_A		MTK_M4U_ID(9, 8)
109 #define M4U_PORT_L9_IMG_IMGI_T1_B		MTK_M4U_ID(9, 9)
110 #define M4U_PORT_L9_IMG_IMGBI_T1_B		MTK_M4U_ID(9, 10)
111 #define M4U_PORT_L9_IMG_IMGCI_T1_B		MTK_M4U_ID(9, 11)
112 #define M4U_PORT_L9_IMG_YUVO_T5_A		MTK_M4U_ID(9, 12)
113 #define M4U_PORT_L9_IMG_SMTI_T1_B		MTK_M4U_ID(9, 13)
114 #define M4U_PORT_L9_IMG_TNCSO_T1_A		MTK_M4U_ID(9, 14)
115 #define M4U_PORT_L9_IMG_SMTO_T1_A		MTK_M4U_ID(9, 15)
116 #define M4U_PORT_L9_IMG_TNCSTO_T1_A		MTK_M4U_ID(9, 16)
117 #define M4U_PORT_L9_IMG_YUVO_T2_B		MTK_M4U_ID(9, 17)
118 #define M4U_PORT_L9_IMG_YUVO_T5_B		MTK_M4U_ID(9, 18)
119 #define M4U_PORT_L9_IMG_SMTO_T1_B		MTK_M4U_ID(9, 19)
130 #define M4U_PORT_L10_IMG_SMTI_D6_A		MTK_M4U_ID(10, 8)
131 #define M4U_PORT_L10_IMG_PIMGI_P1_A		MTK_M4U_ID(10, 9)
156 #define M4U_PORT_L11_IMG_WPE_TNR_CQ0_A		MTK_M4U_ID(11, 8)
157 #define M4U_PORT_L11_IMG_WPE_TNR_CQ1_A		MTK_M4U_ID(11, 9)
168 #define M4U_PORT_L12_IMG_DVP_RDMA		MTK_M4U_ID(12, 8)
169 #define M4U_PORT_L12_IMG_DVP_WDMA		MTK_M4U_ID(12, 9)
180 #define M4U_PORT_L13_CAM_PDAI_0			MTK_M4U_ID(13, 8)
181 #define M4U_PORT_L13_CAM_FAKE			MTK_M4U_ID(13, 9)
192 #define M4U_PORT_L14_CAM_IPUO			MTK_M4U_ID(14, 8)
193 #define M4U_PORT_L14_CAM_IPU2O			MTK_M4U_ID(14, 9)
211 #define M4U_PORT_L16_CAM_UFDI_R3		MTK_M4U_ID(16, 8)
212 #define M4U_PORT_L16_CAM_RAWI_R4		MTK_M4U_ID(16, 9)
244 #define M4U_PORT_L19_JPGENC_C_RDMA		MTK_M4U_ID(19, 8)
245 #define M4U_PORT_L19_JPGENC_Q_TABLE		MTK_M4U_ID(19, 9)
273 #define M4U_PORT_L20_JPGENC_C_RDMA		MTK_M4U_ID(20, 8)
274 #define M4U_PORT_L20_JPGENC_Q_TABLE		MTK_M4U_ID(20, 9)
302 #define M4U_PORT_L21_VDEC_VLD2_EXT		MTK_M4U_ID(21, 8)
303 #define M4U_PORT_L21_VDEC_AVC_MV_EXT		MTK_M4U_ID(21, 9)
314 #define M4U_PORT_L22_VDEC_VLD2_EXT		MTK_M4U_ID(22, 8)
315 #define M4U_PORT_L22_VDEC_AVC_MV_EXT		MTK_M4U_ID(22, 9)
330 #define M4U_PORT_L24_VDEC_LAT1_AVC_MC_EXT	MTK_M4U_ID(24, 8)
331 #define M4U_PORT_L24_VDEC_LAT1_PRED_RD_EXT	MTK_M4U_ID(24, 9)
344 #define M4U_PORT_L25_CAM_MRAW2_IMGO_M1		MTK_M4U_ID(25, 8)
345 #define M4U_PORT_L25_CAM_MRAW2_IMGBO_M1		MTK_M4U_ID(25, 9)
358 #define M4U_PORT_L26_CAM_MRAW3_IMGO_M1		MTK_M4U_ID(26, 8)
359 #define M4U_PORT_L26_CAM_MRAW3_IMGBO_M1		MTK_M4U_ID(26, 9)
372 #define M4U_PORT_L27_CAM_UFDI_R3		MTK_M4U_ID(27, 8)
373 #define M4U_PORT_L27_CAM_RAWI_R4		MTK_M4U_ID(27, 9)