Lines Matching +full:5 +full:g
13 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
16 * b) The iova of any master can NOT cross the 4G/8G/12G boundary.
21 * disp 0 ~ 4G larb0/1/2/3
22 * vcodec 4G ~ 8G larb19/20/21/22/23/24
23 * cam/mdp 8G ~ 12G the other larbs.
24 * N/A 12G ~ 16G
29 * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
40 #define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 5)
48 #define M4U_PORT_L1_DISP_FAKE0 MTK_M4U_ID(1, 5)
63 #define M4U_PORT_L3_HDR_ADL MTK_M4U_ID(3, 5)
74 #define M4U_PORT_L5_SVPP1_MDP_RDMA MTK_M4U_ID(5, 0)
75 #define M4U_PORT_L5_SVPP1_MDP_FG MTK_M4U_ID(5, 1)
76 #define M4U_PORT_L5_SVPP1_MDP_OVL MTK_M4U_ID(5, 2)
77 #define M4U_PORT_L5_SVPP1_MDP_WROT MTK_M4U_ID(5, 3)
78 #define M4U_PORT_L5_SVPP2_MDP_RDMA MTK_M4U_ID(5, 4)
79 #define M4U_PORT_L5_SVPP2_MDP_FG MTK_M4U_ID(5, 5)
80 #define M4U_PORT_L5_SVPP2_MDP_WROT MTK_M4U_ID(5, 6)
81 #define M4U_PORT_L5_FAKE MTK_M4U_ID(5, 7)
105 #define M4U_PORT_L9_IMG_TNCSTI_T4_A MTK_M4U_ID(9, 5)
127 #define M4U_PORT_L10_IMG_TNRWI_D1_A MTK_M4U_ID(10, 5)
153 #define M4U_PORT_L11_IMG_WPE_TNR_WDMA0_A MTK_M4U_ID(11, 5)
165 #define M4U_PORT_L12_IMG_ME_WDMA MTK_M4U_ID(12, 5)
177 #define M4U_PORT_L13_CAM_GCAMSV_B_IMGO_1 MTK_M4U_ID(13, 5)
189 #define M4U_PORT_L14_CAM_SCAMSV_B_IMGO_1 MTK_M4U_ID(14, 5)
208 #define M4U_PORT_L16_CAM_RAWI_R2 MTK_M4U_ID(16, 5)
226 #define M4U_PORT_L17_CAM_DRZS4NO_R1 MTK_M4U_ID(17, 5)
241 #define M4U_PORT_L19_VENC_NBM_RDMA MTK_M4U_ID(19, 5)
270 #define M4U_PORT_L20_VENC_NBM_RDMA MTK_M4U_ID(20, 5)
299 #define M4U_PORT_L21_VDEC_PPWRAP_EXT MTK_M4U_ID(21, 5)
311 #define M4U_PORT_L22_VDEC_PPWRAP_EXT MTK_M4U_ID(22, 5)
327 #define M4U_PORT_L24_VDEC_LAT0_WDMA_EXT MTK_M4U_ID(24, 5)
341 #define M4U_PORT_L25_CAM_MRAW2_LSCI_M1 MTK_M4U_ID(25, 5)
355 #define M4U_PORT_L26_CAM_MRAW3_LSCI_M1 MTK_M4U_ID(26, 5)
369 #define M4U_PORT_L27_CAM_RAWI_R2 MTK_M4U_ID(27, 5)
387 #define M4U_PORT_L28_CAM_DRZS4NO_R1 MTK_M4U_ID(28, 5)