dt-bindings/memory/mt8195-memory-port.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <dt-bindings/memory/mtk-memory-port.h>
20  * modules    dma-address-region	larbs-ports
21  * disp         0 ~ 4G                  larb0/1/2/3
26  * CCU1   0x24400_0000 ~ 0x247ff_ffff   larb18: port 2/3
29  * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
30  * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27
38 #define M4U_PORT_L0_DISP_OVL0_RDMA1		MTK_M4U_ID(0, 3)
46 #define M4U_PORT_L1_DISP_OVL0_RDMA1		MTK_M4U_ID(1, 3)
54 #define M4U_PORT_L2_MDP_RDMA6			MTK_M4U_ID(2, 3)
58 #define M4U_PORT_L3_MDP_RDMA1			MTK_M4U_ID(3, 0)
59 #define M4U_PORT_L3_MDP_RDMA3			MTK_M4U_ID(3, 1)
60 #define M4U_PORT_L3_MDP_RDMA5			MTK_M4U_ID(3, 2)
61 #define M4U_PORT_L3_MDP_RDMA7			MTK_M4U_ID(3, 3)
62 #define M4U_PORT_L3_HDR_DS			MTK_M4U_ID(3, 4)
63 #define M4U_PORT_L3_HDR_ADL			MTK_M4U_ID(3, 5)
64 #define M4U_PORT_L3_DISP_FAKE1			MTK_M4U_ID(3, 6)
70 #define M4U_PORT_L4_MDP_WROT			MTK_M4U_ID(4, 3)
77 #define M4U_PORT_L5_SVPP1_MDP_WROT		MTK_M4U_ID(5, 3)
87 #define M4U_PORT_L6_FAKE			MTK_M4U_ID(6, 3)
100 #define M4U_PORT_L9_IMG_IMGI_T1_A		MTK_M4U_ID(9, 0)
101 #define M4U_PORT_L9_IMG_IMGBI_T1_A		MTK_M4U_ID(9, 1)
102 #define M4U_PORT_L9_IMG_IMGCI_T1_A		MTK_M4U_ID(9, 2)
103 #define M4U_PORT_L9_IMG_SMTI_T1_A		MTK_M4U_ID(9, 3)
104 #define M4U_PORT_L9_IMG_TNCSTI_T1_A		MTK_M4U_ID(9, 4)
105 #define M4U_PORT_L9_IMG_TNCSTI_T4_A		MTK_M4U_ID(9, 5)
106 #define M4U_PORT_L9_IMG_YUVO_T1_A		MTK_M4U_ID(9, 6)
107 #define M4U_PORT_L9_IMG_TIMGO_T1_A		MTK_M4U_ID(9, 7)
108 #define M4U_PORT_L9_IMG_YUVO_T2_A		MTK_M4U_ID(9, 8)
109 #define M4U_PORT_L9_IMG_IMGI_T1_B		MTK_M4U_ID(9, 9)
110 #define M4U_PORT_L9_IMG_IMGBI_T1_B		MTK_M4U_ID(9, 10)
111 #define M4U_PORT_L9_IMG_IMGCI_T1_B		MTK_M4U_ID(9, 11)
112 #define M4U_PORT_L9_IMG_YUVO_T5_A		MTK_M4U_ID(9, 12)
113 #define M4U_PORT_L9_IMG_SMTI_T1_B		MTK_M4U_ID(9, 13)
114 #define M4U_PORT_L9_IMG_TNCSO_T1_A		MTK_M4U_ID(9, 14)
115 #define M4U_PORT_L9_IMG_SMTO_T1_A		MTK_M4U_ID(9, 15)
116 #define M4U_PORT_L9_IMG_TNCSTO_T1_A		MTK_M4U_ID(9, 16)
117 #define M4U_PORT_L9_IMG_YUVO_T2_B		MTK_M4U_ID(9, 17)
118 #define M4U_PORT_L9_IMG_YUVO_T5_B		MTK_M4U_ID(9, 18)
119 #define M4U_PORT_L9_IMG_SMTO_T1_B		MTK_M4U_ID(9, 19)
125 #define M4U_PORT_L10_IMG_DMGI_D1_A		MTK_M4U_ID(10, 3)
131 #define M4U_PORT_L10_IMG_PIMGI_P1_A		MTK_M4U_ID(10, 9)
151 #define M4U_PORT_L11_IMG_WPE_TNR_RDMA0_A	MTK_M4U_ID(11, 3)
157 #define M4U_PORT_L11_IMG_WPE_TNR_CQ1_A		MTK_M4U_ID(11, 9)
163 #define M4U_PORT_L12_IMG_FDVT_WRB		MTK_M4U_ID(12, 3)
169 #define M4U_PORT_L12_IMG_DVP_WDMA		MTK_M4U_ID(12, 9)
175 #define M4U_PORT_L13_CAM_SCAMSV_A_IMGO_0	MTK_M4U_ID(13, 3)
181 #define M4U_PORT_L13_CAM_FAKE			MTK_M4U_ID(13, 9)
187 #define M4U_PORT_L14_CAM_GCAMSV_B_IMGO_1	MTK_M4U_ID(14, 3)
193 #define M4U_PORT_L14_CAM_IPU2O			MTK_M4U_ID(14, 9)
206 #define M4U_PORT_L16_CAM_BPCI_R1		MTK_M4U_ID(16, 3)
212 #define M4U_PORT_L16_CAM_RAWI_R4		MTK_M4U_ID(16, 9)
224 #define M4U_PORT_L17_CAM_YUVO_R2		MTK_M4U_ID(17, 3)
233 #define M4U_PORT_L18_CAM_CCUO2			MTK_M4U_ID(18, 3)
239 #define M4U_PORT_L19_VENC_SV_COMV		MTK_M4U_ID(19, 3)
245 #define M4U_PORT_L19_JPGENC_Q_TABLE		MTK_M4U_ID(19, 9)
268 #define M4U_PORT_L20_VENC_SV_COMV		MTK_M4U_ID(20, 3)
274 #define M4U_PORT_L20_JPGENC_Q_TABLE		MTK_M4U_ID(20, 9)
297 #define M4U_PORT_L21_VDEC_PRED_RD_EXT		MTK_M4U_ID(21, 3)
303 #define M4U_PORT_L21_VDEC_AVC_MV_EXT		MTK_M4U_ID(21, 9)
309 #define M4U_PORT_L22_VDEC_PRED_RD_EXT		MTK_M4U_ID(22, 3)
315 #define M4U_PORT_L22_VDEC_AVC_MV_EXT		MTK_M4U_ID(22, 9)
325 #define M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT	MTK_M4U_ID(24, 3)
331 #define M4U_PORT_L24_VDEC_LAT1_PRED_RD_EXT	MTK_M4U_ID(24, 9)
339 #define M4U_PORT_L25_CAM_MRAW0_IMGO_M1		MTK_M4U_ID(25, 3)
345 #define M4U_PORT_L25_CAM_MRAW2_IMGBO_M1		MTK_M4U_ID(25, 9)
353 #define M4U_PORT_L26_CAM_MRAW1_IMGO_M1		MTK_M4U_ID(26, 3)
359 #define M4U_PORT_L26_CAM_MRAW3_IMGBO_M1		MTK_M4U_ID(26, 9)
367 #define M4U_PORT_L27_CAM_BPCI_R1		MTK_M4U_ID(27, 3)
373 #define M4U_PORT_L27_CAM_RAWI_R4		MTK_M4U_ID(27, 9)
385 #define M4U_PORT_L28_CAM_YUVO_R2		MTK_M4U_ID(28, 3)