dt-bindings/memory/mt8195-memory-port.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <dt-bindings/memory/mtk-memory-port.h>
20  * modules    dma-address-region	larbs-ports
29  * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
30  * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27
118 #define M4U_PORT_L9_IMG_YUVO_T5_B		MTK_M4U_ID(9, 18)
140 #define M4U_PORT_L10_IMG_FEO_D1_A		MTK_M4U_ID(10, 18)
230 #define M4U_PORT_L18_CAM_CCUI			MTK_M4U_ID(18, 0)
231 #define M4U_PORT_L18_CAM_CCUO			MTK_M4U_ID(18, 1)
232 #define M4U_PORT_L18_CAM_CCUI2			MTK_M4U_ID(18, 2)
233 #define M4U_PORT_L18_CAM_CCUO2			MTK_M4U_ID(18, 3)
254 #define M4U_PORT_L19_JPGDEC_WDMA1		MTK_M4U_ID(19, 18)
261 #define M4U_PORT_L19_VENC_REF_CHROMA		MTK_M4U_ID(19, 25)
283 #define M4U_PORT_L20_JPGDEC_WDMA1		MTK_M4U_ID(20, 18)
290 #define M4U_PORT_L20_VENC_REF_CHROMA		MTK_M4U_ID(20, 25)
336 #define M4U_PORT_L25_CAM_MRAW0_LSCI_M1		MTK_M4U_ID(25, 0)
337 #define M4U_PORT_L25_CAM_MRAW0_CQI_M1		MTK_M4U_ID(25, 1)
338 #define M4U_PORT_L25_CAM_MRAW0_CQI_M2		MTK_M4U_ID(25, 2)
339 #define M4U_PORT_L25_CAM_MRAW0_IMGO_M1		MTK_M4U_ID(25, 3)
340 #define M4U_PORT_L25_CAM_MRAW0_IMGBO_M1		MTK_M4U_ID(25, 4)
341 #define M4U_PORT_L25_CAM_MRAW2_LSCI_M1		MTK_M4U_ID(25, 5)
342 #define M4U_PORT_L25_CAM_MRAW2_CQI_M1		MTK_M4U_ID(25, 6)
343 #define M4U_PORT_L25_CAM_MRAW2_CQI_M2		MTK_M4U_ID(25, 7)
344 #define M4U_PORT_L25_CAM_MRAW2_IMGO_M1		MTK_M4U_ID(25, 8)
345 #define M4U_PORT_L25_CAM_MRAW2_IMGBO_M1		MTK_M4U_ID(25, 9)
346 #define M4U_PORT_L25_CAM_MRAW0_AFO_M1		MTK_M4U_ID(25, 10)
347 #define M4U_PORT_L25_CAM_MRAW2_AFO_M1		MTK_M4U_ID(25, 11)
394 #define IOMMU_PORT_INFRA_PCIE0			MTK_IFAIOMMU_PERI_ID(18)
400 #define IOMMU_PORT_INFRA_SSUSB_P1_1_W		MTK_IFAIOMMU_PERI_ID(25)