dt-bindings/memory/mt8195-memory-port.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <dt-bindings/memory/mtk-memory-port.h>
20  * modules    dma-address-region	larbs-ports
21  * disp         0 ~ 4G                  larb0/1/2/3
26  * CCU1   0x24400_0000 ~ 0x247ff_ffff   larb18: port 2/3
29  * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
30  * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27
37 #define M4U_PORT_L0_DISP_OVL0_RDMA0		MTK_M4U_ID(0, 2)
45 #define M4U_PORT_L1_DISP_OVL0_RDMA0		MTK_M4U_ID(1, 2)
51 #define M4U_PORT_L2_MDP_RDMA0			MTK_M4U_ID(2, 0)
52 #define M4U_PORT_L2_MDP_RDMA2			MTK_M4U_ID(2, 1)
53 #define M4U_PORT_L2_MDP_RDMA4			MTK_M4U_ID(2, 2)
54 #define M4U_PORT_L2_MDP_RDMA6			MTK_M4U_ID(2, 3)
55 #define M4U_PORT_L2_DISP_FAKE1			MTK_M4U_ID(2, 4)
60 #define M4U_PORT_L3_MDP_RDMA5			MTK_M4U_ID(3, 2)
69 #define M4U_PORT_L4_MDP_OVL			MTK_M4U_ID(4, 2)
76 #define M4U_PORT_L5_SVPP1_MDP_OVL		MTK_M4U_ID(5, 2)
86 #define M4U_PORT_L6_SVPP3_MDP_WROT		MTK_M4U_ID(6, 2)
92 #define M4U_PORT_L7_IMG_WPE_WDMA0		MTK_M4U_ID(7, 2)
97 #define M4U_PORT_L8_IMG_WPE_WDMA0		MTK_M4U_ID(8, 2)
100 #define M4U_PORT_L9_IMG_IMGI_T1_A		MTK_M4U_ID(9, 0)
101 #define M4U_PORT_L9_IMG_IMGBI_T1_A		MTK_M4U_ID(9, 1)
102 #define M4U_PORT_L9_IMG_IMGCI_T1_A		MTK_M4U_ID(9, 2)
103 #define M4U_PORT_L9_IMG_SMTI_T1_A		MTK_M4U_ID(9, 3)
104 #define M4U_PORT_L9_IMG_TNCSTI_T1_A		MTK_M4U_ID(9, 4)
105 #define M4U_PORT_L9_IMG_TNCSTI_T4_A		MTK_M4U_ID(9, 5)
106 #define M4U_PORT_L9_IMG_YUVO_T1_A		MTK_M4U_ID(9, 6)
107 #define M4U_PORT_L9_IMG_TIMGO_T1_A		MTK_M4U_ID(9, 7)
108 #define M4U_PORT_L9_IMG_YUVO_T2_A		MTK_M4U_ID(9, 8)
109 #define M4U_PORT_L9_IMG_IMGI_T1_B		MTK_M4U_ID(9, 9)
110 #define M4U_PORT_L9_IMG_IMGBI_T1_B		MTK_M4U_ID(9, 10)
111 #define M4U_PORT_L9_IMG_IMGCI_T1_B		MTK_M4U_ID(9, 11)
112 #define M4U_PORT_L9_IMG_YUVO_T5_A		MTK_M4U_ID(9, 12)
113 #define M4U_PORT_L9_IMG_SMTI_T1_B		MTK_M4U_ID(9, 13)
114 #define M4U_PORT_L9_IMG_TNCSO_T1_A		MTK_M4U_ID(9, 14)
115 #define M4U_PORT_L9_IMG_SMTO_T1_A		MTK_M4U_ID(9, 15)
116 #define M4U_PORT_L9_IMG_TNCSTO_T1_A		MTK_M4U_ID(9, 16)
117 #define M4U_PORT_L9_IMG_YUVO_T2_B		MTK_M4U_ID(9, 17)
118 #define M4U_PORT_L9_IMG_YUVO_T5_B		MTK_M4U_ID(9, 18)
119 #define M4U_PORT_L9_IMG_SMTO_T1_B		MTK_M4U_ID(9, 19)
124 #define M4U_PORT_L10_IMG_DEPI_D1_A		MTK_M4U_ID(10, 2)
131 #define M4U_PORT_L10_IMG_PIMGI_P1_A		MTK_M4U_ID(10, 9)
150 #define M4U_PORT_L11_IMG_WPE_EIS_WDMA0_A	MTK_M4U_ID(11, 2)
157 #define M4U_PORT_L11_IMG_WPE_TNR_CQ1_A		MTK_M4U_ID(11, 9)
162 #define M4U_PORT_L12_IMG_FDVT_WRA		MTK_M4U_ID(12, 2)
169 #define M4U_PORT_L12_IMG_DVP_WDMA		MTK_M4U_ID(12, 9)
174 #define M4U_PORT_L13_CAM_GCAMSV_A_IMGO_0	MTK_M4U_ID(13, 2)
181 #define M4U_PORT_L13_CAM_FAKE			MTK_M4U_ID(13, 9)
186 #define M4U_PORT_L14_CAM_GCAMSV_B_IMGO_0	MTK_M4U_ID(14, 2)
193 #define M4U_PORT_L14_CAM_IPU2O			MTK_M4U_ID(14, 9)
205 #define M4U_PORT_L16_CAM_CQI_R2			MTK_M4U_ID(16, 2)
212 #define M4U_PORT_L16_CAM_RAWI_R4		MTK_M4U_ID(16, 9)
223 #define M4U_PORT_L17_CAM_YUVCO_R1		MTK_M4U_ID(17, 2)
232 #define M4U_PORT_L18_CAM_CCUI2			MTK_M4U_ID(18, 2)
238 #define M4U_PORT_L19_VENC_BSDMA			MTK_M4U_ID(19, 2)
245 #define M4U_PORT_L19_JPGENC_Q_TABLE		MTK_M4U_ID(19, 9)
267 #define M4U_PORT_L20_VENC_BSDMA			MTK_M4U_ID(20, 2)
274 #define M4U_PORT_L20_JPGENC_Q_TABLE		MTK_M4U_ID(20, 9)
296 #define M4U_PORT_L21_VDEC_PP_EXT		MTK_M4U_ID(21, 2)
303 #define M4U_PORT_L21_VDEC_AVC_MV_EXT		MTK_M4U_ID(21, 9)
308 #define M4U_PORT_L22_VDEC_PP_EXT		MTK_M4U_ID(22, 2)
315 #define M4U_PORT_L22_VDEC_AVC_MV_EXT		MTK_M4U_ID(22, 9)
324 #define M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT	MTK_M4U_ID(24, 2)
331 #define M4U_PORT_L24_VDEC_LAT1_PRED_RD_EXT	MTK_M4U_ID(24, 9)
338 #define M4U_PORT_L25_CAM_MRAW0_CQI_M2		MTK_M4U_ID(25, 2)
345 #define M4U_PORT_L25_CAM_MRAW2_IMGBO_M1		MTK_M4U_ID(25, 9)
352 #define M4U_PORT_L26_CAM_MRAW1_CQI_M2		MTK_M4U_ID(26, 2)
359 #define M4U_PORT_L26_CAM_MRAW3_IMGBO_M1		MTK_M4U_ID(26, 9)
366 #define M4U_PORT_L27_CAM_CQI_R2			MTK_M4U_ID(27, 2)
373 #define M4U_PORT_L27_CAM_RAWI_R4		MTK_M4U_ID(27, 9)
384 #define M4U_PORT_L28_CAM_YUVCO_R1		MTK_M4U_ID(28, 2)