Lines Matching +full:0 +full:- +full:19
1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <dt-bindings/memory/mtk-memory-port.h>
13 * 0 ~ 4G; 4G ~ 8G; 8G ~ 12G; 12G ~ 16G, we could adjust these masters
20 * modules dma-address-region larbs-ports
21 * disp 0 ~ 4G larb0/1/2/3
25 * CCU0 0x24000_0000 ~ 0x243ff_ffff larb18: port 0/1
26 * CCU1 0x24400_0000 ~ 0x247ff_ffff larb18: port 2/3
29 * iommu-vdo: larb0/2/5/7/9/10/11/13/17/19/21/24/25/28
30 * iommu-vpp: larb1/3/4/6/8/12/14/16/18/20/22/23/26/27
35 #define M4U_PORT_L0_DISP_RDMA0 MTK_M4U_ID(0, 0)
36 #define M4U_PORT_L0_DISP_WDMA0 MTK_M4U_ID(0, 1)
37 #define M4U_PORT_L0_DISP_OVL0_RDMA0 MTK_M4U_ID(0, 2)
38 #define M4U_PORT_L0_DISP_OVL0_RDMA1 MTK_M4U_ID(0, 3)
39 #define M4U_PORT_L0_DISP_OVL0_HDR MTK_M4U_ID(0, 4)
40 #define M4U_PORT_L0_DISP_FAKE0 MTK_M4U_ID(0, 5)
43 #define M4U_PORT_L1_DISP_RDMA0 MTK_M4U_ID(1, 0)
51 #define M4U_PORT_L2_MDP_RDMA0 MTK_M4U_ID(2, 0)
58 #define M4U_PORT_L3_MDP_RDMA1 MTK_M4U_ID(3, 0)
67 #define M4U_PORT_L4_MDP_RDMA MTK_M4U_ID(4, 0)
74 #define M4U_PORT_L5_SVPP1_MDP_RDMA MTK_M4U_ID(5, 0)
84 #define M4U_PORT_L6_SVPP3_MDP_RDMA MTK_M4U_ID(6, 0)
90 #define M4U_PORT_L7_IMG_WPE_RDMA0 MTK_M4U_ID(7, 0)
95 #define M4U_PORT_L8_IMG_WPE_RDMA0 MTK_M4U_ID(8, 0)
100 #define M4U_PORT_L9_IMG_IMGI_T1_A MTK_M4U_ID(9, 0)
119 #define M4U_PORT_L9_IMG_SMTO_T1_B MTK_M4U_ID(9, 19)
122 #define M4U_PORT_L10_IMG_IMGI_D1_A MTK_M4U_ID(10, 0)
141 #define M4U_PORT_L10_IMG_IMG2O_D1_A MTK_M4U_ID(10, 19)
148 #define M4U_PORT_L11_IMG_WPE_EIS_RDMA0_A MTK_M4U_ID(11, 0)
160 #define M4U_PORT_L12_IMG_FDVT_RDA MTK_M4U_ID(12, 0)
172 #define M4U_PORT_L13_CAM_CAMSV_CQI_E1 MTK_M4U_ID(13, 0)
184 #define M4U_PORT_L14_CAM_GCAMSV_A_IMGO_1 MTK_M4U_ID(14, 0)
203 #define M4U_PORT_L16_CAM_IMGO_R1 MTK_M4U_ID(16, 0)
221 #define M4U_PORT_L17_CAM_YUVO_R1 MTK_M4U_ID(17, 0)
230 #define M4U_PORT_L18_CAM_CCUI MTK_M4U_ID(18, 0)
236 #define M4U_PORT_L19_VENC_RCPU MTK_M4U_ID(19, 0)
237 #define M4U_PORT_L19_VENC_REC MTK_M4U_ID(19, 1)
238 #define M4U_PORT_L19_VENC_BSDMA MTK_M4U_ID(19, 2)
239 #define M4U_PORT_L19_VENC_SV_COMV MTK_M4U_ID(19, 3)
240 #define M4U_PORT_L19_VENC_RD_COMV MTK_M4U_ID(19, 4)
241 #define M4U_PORT_L19_VENC_NBM_RDMA MTK_M4U_ID(19, 5)
242 #define M4U_PORT_L19_VENC_NBM_RDMA_LITE MTK_M4U_ID(19, 6)
243 #define M4U_PORT_L19_JPGENC_Y_RDMA MTK_M4U_ID(19, 7)
244 #define M4U_PORT_L19_JPGENC_C_RDMA MTK_M4U_ID(19, 8)
245 #define M4U_PORT_L19_JPGENC_Q_TABLE MTK_M4U_ID(19, 9)
246 #define M4U_PORT_L19_VENC_SUB_W_LUMA MTK_M4U_ID(19, 10)
247 #define M4U_PORT_L19_VENC_FCS_NBM_RDMA MTK_M4U_ID(19, 11)
248 #define M4U_PORT_L19_JPGENC_BSDMA MTK_M4U_ID(19, 12)
249 #define M4U_PORT_L19_JPGDEC_WDMA0 MTK_M4U_ID(19, 13)
250 #define M4U_PORT_L19_JPGDEC_BSDMA0 MTK_M4U_ID(19, 14)
251 #define M4U_PORT_L19_VENC_NBM_WDMA MTK_M4U_ID(19, 15)
252 #define M4U_PORT_L19_VENC_NBM_WDMA_LITE MTK_M4U_ID(19, 16)
253 #define M4U_PORT_L19_VENC_FCS_NBM_WDMA MTK_M4U_ID(19, 17)
254 #define M4U_PORT_L19_JPGDEC_WDMA1 MTK_M4U_ID(19, 18)
255 #define M4U_PORT_L19_JPGDEC_BSDMA1 MTK_M4U_ID(19, 19)
256 #define M4U_PORT_L19_JPGDEC_BUFF_OFFSET1 MTK_M4U_ID(19, 20)
257 #define M4U_PORT_L19_JPGDEC_BUFF_OFFSET0 MTK_M4U_ID(19, 21)
258 #define M4U_PORT_L19_VENC_CUR_LUMA MTK_M4U_ID(19, 22)
259 #define M4U_PORT_L19_VENC_CUR_CHROMA MTK_M4U_ID(19, 23)
260 #define M4U_PORT_L19_VENC_REF_LUMA MTK_M4U_ID(19, 24)
261 #define M4U_PORT_L19_VENC_REF_CHROMA MTK_M4U_ID(19, 25)
262 #define M4U_PORT_L19_VENC_SUB_R_CHROMA MTK_M4U_ID(19, 26)
265 #define M4U_PORT_L20_VENC_RCPU MTK_M4U_ID(20, 0)
284 #define M4U_PORT_L20_JPGDEC_BSDMA1 MTK_M4U_ID(20, 19)
294 #define M4U_PORT_L21_VDEC_MC_EXT MTK_M4U_ID(21, 0)
306 #define M4U_PORT_L22_VDEC_MC_EXT MTK_M4U_ID(22, 0)
318 #define M4U_PORT_L23_VDEC_UFO_ENC_EXT MTK_M4U_ID(23, 0)
322 #define M4U_PORT_L24_VDEC_LAT0_VLD_EXT MTK_M4U_ID(24, 0)
336 #define M4U_PORT_L25_CAM_MRAW0_LSCI_M1 MTK_M4U_ID(25, 0)
350 #define M4U_PORT_L26_CAM_MRAW1_LSCI_M1 MTK_M4U_ID(26, 0)
364 #define M4U_PORT_L27_CAM_IMGO_R1 MTK_M4U_ID(27, 0)
382 #define M4U_PORT_L28_CAM_YUVO_R1 MTK_M4U_ID(28, 0)